- //不帶自動預充電讀操作
- //tRCD = 20ns
- //tRP = 20ns
- //tRAS(max) = 12_0000ns, tRAS(min) = 44ns
- //tRC(min) = 66ns
- //clk=50M, 週期 = 20ns
- //預充電 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0010
- //空命令 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0111
- //讀命令 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0101
- //激活命令 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0011
- //BL = 4
- module sdr_r(
- clk,
- rst,
- r_en,
- r_done,
- r_SDR_CLK,
- r_CKE,
- r_CS_N,
- r_RAS_N,
- r_CAS_N,
- r_WE_N,
- r_BA,
- r_SA,
- r_DQM,
- r_DQ
- );
- input clk,rst;
- input r_en;
- inout [15:0] r_DQ;
- output r_done;
- output r_SDR_CLK;
- output r_CKE;
- output r_CS_N;
- output r_RAS_N;
- output r_CAS_N;
- output r_WE_N;
- output [1:0] r_BA;
- output [12:0] r_SA;
- output [1:0] r_DQM;
- reg [3:0] r_cnt;
- reg r_done;
- reg r_CKE;
- reg r_CS_N;
- reg r_RAS_N;
- reg r_CAS_N;
- reg r_WE_N;
- reg [12:0] r_SA;
- reg [1:0] r_DQM;
- reg [1:0] r_BA;
- parameter row = 13'b0_0000_0000_0001; //行地址
- parameter col = 9'b0_0000_0001; //列地址
- parameter bank = 2'b00; //bank地址
- //============================================
- // 序列機
- //============================================
- always@(posedge clk or negedge rst)
- begin
- if(!rst)
- begin
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_CKE <= 1'b0;
- r_done <= 1'b0;
- end
- else
- begin
- case(r_cnt)
- 1:begin //Active
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b0;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_CKE <= 1'b1;
- r_done <= 1'b0;
- r_SA <= row;
- r_BA <= bank;
- end
- 2:begin //Read
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b0;
- r_WE_N <= 1'b1;
- r_CKE <= 1'b1;
- r_done <= 1'b0;
- r_DQM <= 1'b0;
- r_SA <= col;
- r_SA[10] <= 1'b0;
- r_BA <= bank;
- end
- 3:begin //Nop
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_DQM <= 1'b0;
- r_CKE <= 1'b1;
- end
- 4:begin //Nop
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_DQM <= 1'b0;
- r_CKE <= 1'b1;
- end
- 5:begin //Nop
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_DQM <= 1'b0;
- r_CKE <= 1'b1;
- end
- 6:begin //Precharge
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b0;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b0;
- r_CKE <= 1'b1;
- r_done <= 1'b0;
- r_SA[10] <= 1'b1;
- r_BA <= bank;
- end
- 10:begin //結束給Nop命令
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_CKE <= 1'b0;
- r_done <= 1'b1;
- end
- 11:begin //結束給Nop命令
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_CKE <= 1'b0;
- r_done <= 1'b1;
- end
- default:begin //其他給Nop命令
- r_CS_N <= 1'b0;
- r_RAS_N <= 1'b1;
- r_CAS_N <= 1'b1;
- r_WE_N <= 1'b1;
- r_CKE <= 1'b1;
- r_done <= 1'b0;
- end
- endcase
- end
- end
- //============================================
- // 計數器
- //============================================
- always@(posedge clk or negedge rst)
- begin
- if(!rst) r_cnt <= 4'd0;
- else if(r_en & (!r_done))
- begin
- if(r_cnt == 4'd11) r_cnt <= 4'd0;
- else r_cnt <= r_cnt + 4'd1;
- end
- else r_cnt <= r_cnt;
- end
- //============================================
- // SDR_CLK
- //============================================
- assign r_SDR_CLK = ~clk; //相位相差180度
- //============================================
- endmodule