Verilog:HDLBits（练习笔记）

一、VerilogLanguage(1)

1.1、Basics

1.1.1、Simple wire

wire:

Module Declaration

module top_module( input in, output out );

 Solution:

module top_module( input in, output out );
    assign out = in;
endmodule

Submit:

 1.1.2、Simple wire

Four wires:

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

a -> w
b -> x
b -> y
c -> z

Solution:

module top_module( 
    input a,b,c,
    output w,x,y,z );
	assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;
endmodule

Submit:

  1.1.3、Inverter

Notgate:

Create a module that implements a NOT gate.

Solution:

module top_module( input in, output out );
	assign out = ~in;
endmodule

Submit:

1.1.4、AND gate

Andgate:

Create a module that implements an AND gate.

Solution:

module top_module( 
    input a, 
    input b, 
    output out );
	assign out = a & b;
endmodule

 Submit:

1.1.5、NOR gate 

Norgate:

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

Solution:

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a | b);
endmodule

 Submit:

1.1.6、Xnorgate 

Create a module that implements an XNOR gate.

Solution:

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a ^ b);
endmodule

 Submit:

 1.1.7、Declaring wires

Wire decl:

The circuits so far have been simple enough that the outputs are simple functions of the inputs. As circuits become more complex, you will need wires to connect internal components together. When you need to use a wire, you should declare it in the body of the module, somewhere before it is first used. (In the future, you will encounter more types of signals and variables that are also declared the same way, but for now, we'll start with a signal of type wire).

Solution:

 

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    wire wire1;
    wire wire2;
    assign wire1 = a & b;
	assign wire2 = c & d;
    assign out = wire1 | wire2;
    assign out_n = ~out;
endmodule

 Submit:

1.1.8 7458 chip

The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420.

Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.

Solution:

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	wire wire1, wire2, wire3, wire4;
	assign wire1 = p1a & p1b & p1c;
    assign wire2 = p1d & p1e & p1f;
    assign wire3 = p2a & p2b;
    assign wire4 = p2c & p2d;
    assign p1y = wire1 | wire2;
    assign p2y = wire3 | wire4;
endmodule

 Submit: