Verilog HDL测试模块 时序逻辑的测试模块
实验一:Verilog HDL测试模块
1.实验目的:测试
2.实验内容:Verilog HDL测试模板
3.实验代码:
module decoder3x8(din, en, dout, ex);
input [2:0] din;
input en;
output [7:0] dout;
output ex;
reg [7:0] dout;
reg ex;
always @(din or en)
if(en)
begin
dout=8’b1111_1111;
ex=1’b1;
end
else
begin
case(din)
3’b000: begin
dout=8’b1111_1110;
ex=1’b0;
end
3’b001: begin
dout=8’b1111_1101;
ex=1’b0;
end
3’b010: begin
dout=8’b1111_1011;
ex=1’b0;
end
3’b011: begin
dout=8’b1111_0111;
ex=1’b0;
end
3’b100: begin
dout=8’b1110_1111;
ex=1’b0;
end
3’b101: begin
dout=8’b1101_1111;
ex=1’b0;
end
3’b110: begin
dout=8’b1011_1111;
ex=1’b0;
end
3’b111: begin
dout=8’b0111_1111;
ex=1’b0;
end
default:begin
dout=8’b1111_1111;
ex=1’b0;
end
endcase
end
endmodule
module tbdecoder;
reg [2:0] din;
reg en;
wire [7:0] dout;
wire ex;
initial
begin
#10 en=0;din=3’b000;
#10 en=0;din=3’b001;
#10 en=0;din=3’b010;
#10 en=0;din=3’b011;
#10 en=0;din=3’b100;
#10 en=0;din=3’b101;
#10 en=0;din=3’b110;
#10 en=0;din=3’b111;
#10 en=0;din=3’b1x1;
#10 en=0;din=3’b000;
#10 en=0;din=3’b001;
#10 en=0;din=3’b010;
#10 en=0;din=3’b011;
#10 en=0;din=3’b100;
#10 en=0;din=3’b101;
#10 en=0;din=3’b110;
#10 en=0;din=3’b111;
#10 $stop;
end
decoder3x8 idecoder(din, en, dout, ex);
endmodule
4.实验视频:1.00 UYm:/ Verilog HDL测试模块;¢¢Puu56dWovj8¢¢复制咑幵抖音搜索
5.实验结果:
实验二:时序逻辑的测试模板
1.实验目的:检验代码
2.实验内容:时序逻辑的测试模板
3.实验代码:
module p2s(data_in,clock,reset,load,data_out,done);
input [3:0] data_in;
input clock,reset,load;
output data_out;
output done;
reg done;
reg [3:0] temp;
reg [3:0] cnt;
always@ (posedge clock or posedge reset )
begin
if(reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if(load)
begin
temp<=data_in;
cnt<=0;
done<=0;
end
else if(cnt==3)
begin
temp <= {temp [2:0],1’b0};
cnt<=0;
done<=1;
end
else
begin
temp <= {temp[2:0],1’b0};
cnt<=cnt+1;
done<=0;
end
end
assign data_out=(done==1) ?1'bz:temp[3];
endmodule
4.实验视频:1.56 CUY:/ 时序逻辑的测试模块;ππ2CAVcBIovj8ππ复製打幵抖yīΠ搜索
5.实验结果: