2021-06-11

最新推荐文章于 2022-03-29 16:23:59 发布

weixin_58727007

最新推荐文章于 2022-03-29 16:23:59 发布

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分类专栏：笔记

本文链接：https://blog.csdn.net/weixin_58727007/article/details/117815183

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该博客介绍了如何下载QuartusII和ModelSim软件，并通过实例代码演示了如何进行FPGA联合仿真的具体步骤。实验包括编写RS触发器、状态机和除法器的Verilog代码，以及使用B站视频教程进行指导。实验截图和视频链接提供了清晰的操作过程，供读者参考学习。

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.实验目的：
下载Quartur ii软件和modlsim并进行联合仿真。

2.实验内容：
参照哔哩哔哩中教程的代码，然后用quartus ii和modlsim进行联合仿真
3.实验原理：按照视频上的内容，书写和运行代码，完成联合仿真操作。

4实验工具：
pc机和Quartur ii软件和modlsim软件。

5.实验截图：
在这里插入图入图片描述描述](https://img-blog.csdnimg.cn/20210611140220527.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl81ODcyNzAwNw==,size_16,color_FFFFFF,t_70)
在这里插入图片描述
6.实验视频：

请下载哔哩哔哩动画打开此网址：
【仿真-哔哩哔哩】https://b23.tv/VUmS3l
7.实验代码：
第一个代码：
module my_rs (reset,set,q,qbar);
input reset,set;
output q,qbar;

nor # (1) n1 (q,reset,qbar);
nor # (1) n2 (qbar,set,q);

endmodule
第二个代码：
module ex8_1(clock,reset,x,y1,y2) ;
input clock,reset;
input x;
output y1,y2;
reg y1,y2;

reg [3:0] cstate,nstate;

parameter s0=4’b0001,s1=4’b0010,
s2=4’b0100,s3=4’b1000;

always @ (posedge clock or posedge reset)
begin
if (reset)
cstate<=s0;
else
cstate<=nstate;
end

always @ (cstate or x)
begin
case (cstate)
s0:begin
if (x0)
nstate=s1;
else
nstate=s3;
end
s1:begin
if (x0)
nstate=s2;
else
nstate=s0;
end
s2:begin
if (x0)
nstate=s3;
else
nstate=s1;
end
s3:begin
if (x0)
nstate=s0;
else
nstate=s2;
end
default : nstate=s0;
endcase
end

always @ (cstate or x)
begin
case (cstate)
s0 : begin
if (x0)
y1=1;
else
y1=0;
end
s1 : begin
if (x0)
y1=0;
else
y1=0;
end
s2 : begin
if (x0)
y1=0;
else
y1=0;
end
s3 : begin
if (x0)
y1=0;
else
y1=1;
end
default :y1=0;
endcase
end

always @ (cstate or x)
begin
if (cstates0 && x0)
y2=1;
else if (cstates3 && x1)
y2=1;
else
y2=0;
end

endmodule
第三个代码：
module div2(clk, reset, start, A, B, D, R, ok, err);
parameter n = 32;
parameter m = 16;

input clk, reset, start;
input [n-1:0] A, B;
output [n+m-1:0] D;
output [n-1:0] R;
output ok, err;

wire invalid, carry, load, run;

div_ctl UCTL(clk, reset, start, invalid, carry, load, run, err, ok);
div_datapath UDATAPATH(clk, reset, A, B, load, run, invalid, carry, D, R);

endmodule

module div_ctl(clk, reset, start, invalid, carry, load, run, err, ok);
parameter n = 32;
parameter m = 16;
parameter STATE_INIT = 3’b001;
parameter STATE_RUN = 3’b010;
parameter STATE_FINISH = 3’b100;
input clk, reset, start, invalid, carry;
output load, run, err, ok;

reg [2:0] current_state, next_state;
reg [5:0] cnt;
reg load, run, err, ok;

always @(posedge clk or negedge reset)
begin
if(!reset) begin
current_state <= STATE_INIT;
cnt <= 0;
end else begin
current_state <= next_state;
if(run) cnt <= cnt + 1’b1;
end
end

always @(posedge clk or negedge reset)
begin
if(!reset) begin
err <= 0;
end else if(next_state==STATE_RUN) begin
if(invalid) err <= 1;
end
end

always @(current_state or start or invalid or carry or cnt)

begin
load <= 1’b0;
ok <= 1’b0;
run <= 1’b0;

  case(current_state)
     STATE_INIT: begin
        if(start) next_state <= STATE_RUN;
        else next_state <= STATE_INIT;
        load <= 1;
     end
     STATE_RUN : begin
        run <= 1;
        if(invalid) begin
           next_state <= STATE_FINISH;   
        end else if(cnt==(n+m-1)) begin
           next_state <= STATE_FINISH;    
        end else begin
           next_state <= STATE_RUN;
        end
     end
     STATE_FINISH : begin
        ok <= 1;
        next_state <= STATE_FINISH;    
     end
     default : begin
        next_state <= STATE_INIT;    
     end
  endcase

end
endmodule

module div_datapath(clk, reset, A, B, load, run, invalid, carry, D, R);
parameter n = 32;
parameter m = 16;
input clk, reset;
input [n-1:0] A, B;
input load, run;
output invalid, carry;
output [n+m-1:0] D;
output [n-1:0] R;

reg [n+n+m-2:0] R0;
reg [n+m-1:0] D;
reg [n-1:0] B0;
reg carry;

wire invalid;
wire [n-1:0] DIFF, R;
wire CO;

assign R = {carry, R0[n+n+m-2:n+m]};
assign invalid = (B0==0);

sub sub(R0[n+n+m-2:n+m-1], B0, 1’b0, DIFF, CO); //ÊµÀý»¯¼õ·¨Æ÷

always @(posedge clk)
begin
if(load) begin //³õÊ¼½×¶Î
D <= 0;
R0 <= {{(n-1){1’b0}}, A, {m{1’b0}}};
B0 <= B;
carry <= 1’b0;
end
else if(run) begin //½áÊø½×¶Î
if(CO && !carry) begin
R0 <= { R0, 1’b0 };
D <= { D[n+m-2:0], 1’b0 };
carry <= R0[n+n+m-2];
end else begin //µü´ú½×¶Î
R0 <= { DIFF, R0[n+m-2:0], 1’b0 };
D <= { D[n+m-2:0], 1’b1 };
carry <= DIFF[n-1];
end
end
end
endmodule

module sub(A, B, CI, DIFF, CO);
parameter n = 32;
input [n-1:0] A, B;
input CI;
output [n-1:0] DIFF;
output CO;

assign {CO, DIFF} = {1’b0, A} - {1’b0, B} - {{n{1’b0}}, CI};
endmodule

8.软件下载网站：
1.复制这段内容后打开百度网盘App，操作更方便哦。链接:https://pan.baidu.com/s/1ZT0ovNAAZ_j3jTGzVCYfbQ
提取码：5jf2
2.复制这段内容后打开百度网盘App，操作更方便哦。链接:https://pan.baidu.com/s/1bkD2-5Gwl1HB6y9hkUF14A 提取码:540y