基于verilog的非级联型分频器设计

最新推荐文章于 2024-06-02 10:35:21 发布

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最新推荐文章于 2024-06-02 10:35:21 发布

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本文链接：https://blog.csdn.net/weixin_59957090/article/details/127166107

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顶层电路

功能：将50Mhz的主频信号分别分频为2hz,1hz,0.5hz,0.25hz,0.2hz,0.125hz的信号

`timescale 1ns/100ps
module time_divide
(
	input clk,
	input rstn,
	output clk2,
	output clk1,
	output clk0p5,
	output clk0p125,
	output clk0p25,
	output clk0p2,
	output [6:0] seg0,
	output [6:0] seg1,
	output [6:0] seg2
);
localparam CNT1Hz = 500;
localparam CNT2Hz = 500/2;
localparam CNT0p5Hz = 1000;
localparam CNT0p125Hz = 4000;
localparam CNT0p25Hz = 2000;
localparam CNT0p2Hz = 2500;



reg [25-1:0] cnt2Hz;
reg [25-1:0]cnt1Hz;
reg [25-1:0]cnt0p5Hz;
reg [25-1:0] cnt0p25Hz;
reg [25-1:0] cnt0p2Hz;
reg [25-1:0] cnt0p125Hz;

wire clk2Hz;
wire clk1Hz;
wire clk0p5Hz;
wire clk0p25Hz;
wire clk0p2Hz;
wire clk0p125Hz;

//  50MHz->2Hz 的分
//assign clk2 = clk2Hz;
//assign clk1 = clk1Hz;
//assign clk0p5 = clk0p5Hz;
//assign clk0p125 = clk0p125Hz;
//assign clk0p25 = clk0p25Hz;
//assign clk0p2 = clk0p2Hz;

// 50MHz -> 2Hz

assign clk2 = (cnt2Hz >= CNT2Hz ) ? 1 : 0;
always @ ( posedge clk )
	begin
		if ( ~rstn )
		cnt2Hz <= 25'd0;
			else
			if ( cnt2Hz >= CNT2Hz*2 )
			cnt2Hz <= 25'd0;
			else
			cnt2Hz <= cnt2Hz +1;
	end

// 2Hz -> 1Hz
assign clk1 = (cnt1Hz >= CNT1Hz)? 1 : 0 ;
always @ ( posedge clk )
	begin
		if ( ~rstn )
		cnt1Hz <= 25'd0;
			else
			if ( cnt1Hz >= CNT1Hz*2 )
			cnt1Hz <= 25'd0;
			else
			cnt1Hz <= cnt1Hz +1;
	end

	// 1Hz -> 0.5Hz
assign clk0p5 = (cnt0p5Hz >= CNT0p5Hz )? 1 : 0 ;
always @ ( posedge clk)
	begin
		if ( ~rstn )
		cnt0p5Hz <= 25'd0;
			else
			if ( cnt0p5Hz >= CNT0p5Hz*2 )
			cnt0p5Hz <= 25'd0;
			else
			cnt0p5Hz <= cnt0p5Hz +1;
	end
	
// 2Hz -> 0.25Hz
assign clk0p25 = (cnt0p25Hz >= CNT0p25Hz )? 1 : 0 ;
always @ ( posedge clk)
	begin
		if ( ~rstn )
		cnt0p25Hz <= 25'd0;
			else
			if ( cnt0p25Hz >= CNT0p25Hz*2 )
			cnt0p25Hz <= 25'd0;
			else
			cnt0p25Hz <= cnt0p25Hz +1;
	end

	// 2Hz -> 0.2Hz
assign clk0p2 = (cnt0p2Hz >= CNT0p2Hz)? 1 : 0 ;    
always @ ( posedge clk)
	begin
		if ( ~rstn )
		cnt0p2Hz <= 25'd0;
			else
			if ( cnt0p2Hz >= CNT0p2Hz*2)
			cnt0p2Hz <= 25'd0;
			else
			cnt0p2Hz <= cnt0p2Hz +1;
	end
	
	// 2Hz -> 0.125Hz
assign clk0p125 = (cnt0p125Hz >= CNT0p125Hz)? 1 : 0 ;    
always @ ( posedge clk)
	begin
		if ( ~rstn )
		cnt0p125Hz <= 25'd0;
			else
			if ( cnt0p125Hz >= CNT0p125Hz*2 )
			cnt0p125Hz <= 25'd0;
			else
			cnt0p125Hz <= cnt0p125Hz +1;
	end
	

endmodule

testbench设计代码

`timescale 1ns/100ps
module test_time_divide;
reg clk=0, rstn=1;
wire clk2, clk1, clk0p5, clk0p25,clk0p2,clk0p125;
initial
begin
#80 rstn = 0;
#200 rstn = 1;
#4000000 $stop;
end
always #10 clk=~clk;
time_divide u3time_divide
(
.rstn(rstn),
.clk(clk),
.clk2(clk2),
.clk1(clk1),
.clk0p5(clk0p5),
.clk0p25(clk0p25),
.clk0p2(clk0p2),
.clk0p125(clk0p125)
);

endmodule