用generate for循环描述8位级联减法器&集成移位寄存器74161

1. 用generate for循环描述8位级联减法器
   另外两个输入xi、yi
   全减器输入来自低位的借位Bi(Borrowinput)
   输出为Di和向高位借位Bo。

Di = Xi xor Y xor Bi
Bo=Xi’Yi’Bi+Xi’YiBi’+Xi’YiBi+XiYiBi
=(XiYi +Xi’Yi’)Bi + Xi’Yi
=Xi’Bi+Xi’Yi+YiBi

module subtractor_8bit(
    input [7:0] X, // 8-bit input X
    input [7:0] Y, // 8-bit input Y
    input B0,      // initial borrow in
    output [7:0] D, // 8-bit output difference
    output B_out    // final borrow out
);
    wire [8:0] B; // Internal borrow wires including B[0] as initial borrow in

    assign B[0] = B0; // assign initial borrow input to B[0]

    genvar i;
    generate
        for (i = 0; i < 8; i = i + 1) begin : full_subtractor
            // Implement the full subtractor logic for each bit
            assign D[i] = X[i] ^ Y[i] ^ B[i]; // Difference bit
            assign B[i+1] = (~X[i] & Y[i]) | (~X[i] & B[i]) | (Y[i] & B[i]); // Borrow out
        end
    endgenerate

    assign B_out = B[8]; // assign the final borrow to B_out

endmodule

2.集成移位寄存器74161

清零	预置	使能	时钟	预置数据输入	输 出
CLRN	LDN	ENP	ENT	CLK	A	B	C	D	QA	QB	QC	QD
L	×	×	×	×	×	×	X	×	L	L	L	L
H	L	×	×	↑	A	B	C	D	A	B	C	D
H	H	L	×	×	×	X	×	×	保持
H	H	×	L	×	×	×	×	×	保持
H	H	H	H	↑	×	×	×	×	保持

module counter_74161 (
  input wire CLRN, // Asynchronous clear
  input wire LDN,  // Load enable
  input wire ENP,  // Enable parallel count
  input wire ENT,  // Enable toggle
  input wire CLK,  // Clock
  input wire [3:0] D, // Parallel data input
  output reg [3:0] Q // Output
);

always @(posedge CLK or negedge CLRN) begin
  if (!CLRN) begin
    Q <= 4'b0000; // Clear the counter
  end else if (!LDN) begin
    Q <= D; // Load the input data into the counter
  end else if (ENP && ENT) begin
    Q <= Q + 1; // Increment the counter if enabled
  end
  // When ENP or ENT is low, the counter holds its value, so no action is needed
end

endmodule