Exams/ece241 2014 q5a
You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.
For example:
AI翻译:
您需要设计一个单输入单输出的串行 2 的补码摩尔状态机。输入(x)是一系列位(每个时钟周期一位),从数字的最低有效位开始,输出(Z)是输入的 2 的补码。该机器将接受任意长度的输入数字。该电路需要一个异步复位。转换在复位释放时开始,在复位断言时停止。
例如:
Exams/ece241 2014 q5b
The following diagram is a Mealy machine implementation of the 2's complementer. Implement using one-hot encoding
AI翻译:
下图是 2 的补码器的 Mealy 机器实现。 实现使用独热编码。
分析:本题难点在于用有限状态构造未知的数量的输入的补码
解决办法:利用补码的特性,从LSB开始直到遇到第一个值为1的编码,它和比它低位的编码不变,在它之上的编码取反。(可以自己举个例子验证一下)
状态转换图如下:
代码如下:
(1)Moore状态机
module top_module (
input clk,
input areset,
input x,
output z );
//状态空间
parameter IDLE = 2'd0;
parameter STATE_ONE = 2'd1;
parameter START_TWO = 2'd2;
//状态寄存器
reg [1:0] state ;
reg [1:0] next_state;
//状态如何转换
always@(*)begin
case(state)
IDLE :next_state=x?STATE_ONE:IDLE;
STATE_ONE:next_state=x?START_TWO:STATE_ONE;
START_TWO:next_state=x?START_TWO:STATE_ONE;
default:;
endcase
end
//状态何时转换
always @(posedge clk or posedge areset) begin
if(areset)
state<=IDLE;
else
state<=next_state;
end
//输出
assign z=(state==STATE_ONE);
endmodule
(2)Mealy 状态机
module top_module (
input clk,
input areset,
input x,
output reg z );
//独热码
parameter IDLE = 2'b01;
parameter STATE_ONE = 2'b10;
//状态寄存
reg [1:0] state ;
reg [1:0] next_state;
//状态如何转换
always@(*)begin
case(state)
IDLE :next_state=x?STATE_ONE:IDLE;
STATE_ONE:next_state=STATE_ONE;
default:;
endcase
end
//状态何时转换
always @(posedge clk or posedge areset) begin
if(areset)
state<=IDLE;
else
state<=next_state;
end
//输出
always @(*) begin
case(state)
IDLE :z=x;
STATE_ONE:z=~x;
endcase
end
endmodule