Verilog HDL设计交通灯求助

设计思路是这样，然后在运行时报错，求助大神

 

module traffic_light(
    input clk,
    input rst,
    input emergency_btn,
    output reg[3:0] east_west,
    output reg[3:0] north_south
);

// 定义状态枚举类型
typedef enum logic[2:0];{
    EAST_WEST_GREEN,
    EAST_WEST_YELLOW,
    EAST_WEST_RED,
    NORTH_SOUTH_GREEN,
    NORTH_SOUTH_YELLOW,
    NORTH_SOUTH_RED,
    EMERGENCY
} state_t;

// 定义状态变量和定时器计数器
state_t state;
integer timer_count;

// 初始化状态和计数器
initial begin
    state = EAST_WEST_RED;
    timer_count = 0;
end// 状态机控制交通信号灯
always @(posedge clk) begin
    if (rst) begin
        state <= EAST_WEST_RED;
        east_west <= 4'b1000;
        north_south <= 4'b0100;
        timer_count <= 0;
    end else begin
        case (state)
            EAST_WEST_GREEN:
                if (timer_count ==