Verilog设计交通灯

1、控制器由状态机编写

module traffic_light (clk,rst_n,count,ew,sn);
	input clk,rst_n;
	input [5:0]count;//count input
	output [2:0] ew,sn;//light
	reg [2:0] ew,sn;
	reg [1:0] pre_state,next_state;
	
	parameter S0=2'b00,
			  S1=2'b01,
			  S2=2'b10,
			  S3=2'b11;
			  
	//state change block
	always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			pre_state<=S0;
		else
			pre_state<=next_state;
	end
	
	//激励方程
	always@(count or pre_state