1.Syntax error
following verilog source has syntax error:
token 'uvm_sequence_item' should be a valid type.please check whether it is misspelled. not visible/valid in the curren context,or not properly imported/exported.
solution:
class trans include在interface前了, 编译不通过.
2.ILLegally driving clocking block output
clocking block output xxxxx is illegally driven by a blocking assignment
solution:
drv clocking 不能使用等号"=" 赋值