分频----vhdl语言将时钟信号分为四种相位

LIBRARY ieee;
USE ieee.std_logic_1164.all;

--  Entity Declaration

ENTITY FOUR_PHASE IS
 -- { {ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 PORT
 (
  CLK : IN STD_LOGIC;
  CLK1 : OUT STD_LOGIC;
  CLK2 : OUT STD_LOGIC;
  CLK3 : OUT STD_LOGIC;
  CLK4 : OUT STD_LOGIC
 );
 -- { {ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 
END FOUR_PHASE;

--  Architecture Body

ARCHITECTURE FOUR_PHASE_architecture OF FOUR_PHASE IS
BEGIN
  PROCESS(CLK)
    VARIABLE COUNT:INTEGER RANGE 0 TO 8:=0 ;
  BEGIN
    IF(CLK'EVENT AND CLK='1') THEN
       COUNT:=COUNT+1;
 END IF;
      CASE COUNT IS
     WHEN 0=> NULL;
       WHEN 1=> CLK1<='0';CLK2<='1';CLK3<='1';CLK4<='0';
       WHEN 2=> CLK1<='0';CLK2<='1&#