利用Xilinx FPGA进行DDR3读写控制总结(三)

最新推荐文章于 2023-11-08 21:39:14 发布
最新推荐文章于 2023-11-08 21:39:14 发布
阅读量2.5k 收藏 36
点赞数 9
分类专栏： DDR3 Xilinx FPGA
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/wnazhe45/article/details/111195657
版权
FPGA 同时被 3 个专栏收录
6 篇文章 5 订阅
订阅专栏
DDR3
3 篇文章 2 订阅
订阅专栏
Xilinx
3 篇文章 0 订阅
订阅专栏

修改example工程代码

    由于官方产生的MIG控制核示例仿真工程太过复杂,不利于新手学习,所以对示例工程进行修改,使之适合学习以及仿真测试.

    该项目完成的是先对DDR3中8个banks的前800个地址执行写操作,8个banks的前800个地址写满之后再对其中数据进行读操作.

    这里需要注意的是app_wdf_data和app_rd_data的位宽,因为Burst Length为8所以这里app_wdf_data和app_rd_data的位宽为16*8=128bits.所以在ui_clk为200MHz下一次时钟上升沿向MIG控制器传输或得到128bits的数据.

    下面给出读写状态控制的代码,完整工程在百度云中,链接:https://pan.baidu.com/s/1sWY0wa-pUvom76pLenC9Ow 提取码：6kab

reg [4:0] cstate,nstate;  //state machine变量
  //写标志 
  wire wr1_done;
  wire wr2_done;
  wire wr3_done;
  wire wr4_done;
  wire wr5_done;
  wire wr6_done;
  wire wr7_done;
  wire wr8_done;
  //读标志             
  wire rd1_done;
  wire rd2_done;
  wire rd3_done;
  wire rd4_done;
  wire rd5_done;
  wire rd6_done;
  wire rd7_done;
  wire rd8_done;
  
  localparam IDLE  = 5'd0,
             WR1   = 5'd1,
             WR2   = 5'd2,
             WR3   = 5'd3,
             WR4   = 5'd4,
             WR5   = 5'd5,
             WR6   = 5'd6,
             WR7   = 5'd7,
             WR8   = 5'd8,
             RD1   = 5'd9,
             RD2   = 5'd10,
             RD3   = 5'd11,
             RD4   = 5'd12,
             RD5   = 5'd13,
             RD6   = 5'd14,
             RD7   = 5'd15,
             RD8   = 5'd16,
             DONE  = 5'd17;  
  //地址变量
  reg [2:0] bank;
  reg [24:0] addr;
  //写数据变量
  reg [15:0] cout16_1;
  reg [15:0] cout16_2;
  reg [15:0] cout16_3;
  reg [15:0] cout16_4;
  reg [15:0] cout16_5;
  reg [15:0] cout16_6;
  reg [15:0] cout16_7;
  reg [15:0] cout16_8;      
  //MIG不需要的引脚置0
  assign app_addr ={1'b0,bank,addr};  
  assign  app_sr_req = 1'b0;
  assign app_ref_req = 1'b0;
  assign app_zq_req  = 1'b0;
  assign app_wdf_mask = 16'h0000;
  assign app_wdf_end = app_wdf_wren;    
  //写标志置位
  assign wr1_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b000) ? 1'b1:1'b0;
  assign wr2_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b001) ? 1'b1:1'b0;
  assign wr3_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b010) ? 1'b1:1'b0;
  assign wr4_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b011) ? 1'b1:1'b0;
  assign wr5_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b100) ? 1'b1:1'b0;
  assign wr6_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b101) ? 1'b1:1'b0;
  assign wr7_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b110) ? 1'b1:1'b0;
  assign wr8_done = (app_cmd ==`CMD_WR && addr == 28'd800 && bank == 3'b111) ? 1'b1:1'b0;
  //读标志置位
  assign rd1_done = (cstate == RD1 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign rd2_done = (cstate == RD2 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign rd3_done = (cstate == RD3 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign rd4_done = (cstate == RD4 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign rd5_done = (cstate == RD5 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign rd6_done = (cstate == RD6 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign rd7_done = (cstate == RD7 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign rd8_done = (cstate == RD8 && app_cmd ==`CMD_RD && addr == 28'd800) ? 1'b1:1'b0;
  assign app_wdf_data = {cout16_1,cout16_2,cout16_3,cout16_4,cout16_5,cout16_6,cout16_7,cout16_8};
  
  assign app_en =(((cstate == WR1 ||cstate == WR2 ||cstate == WR3 ||cstate == WR4 ||cstate == WR5 ||cstate == WR6 ||cstate == WR7 ||cstate == WR8)&& app_wdf_rdy == 1'b1&&app_rdy == 1'b1)
  ||((cstate == RD1 ||cstate == RD2 ||cstate == RD3 ||cstate == RD4 ||cstate == RD5 ||cstate == RD6 ||cstate == RD7 ||cstate == RD8)&& app_rdy == 1'b1)
  &&((!wr1_done)||(!wr2_done)||(!wr3_done)||(!wr4_done)||(!wr5_done)||(!wr6_done)||(!wr7_done)||(!wr8_done)||(!rd1_done)||(!rd2_done)||(!rd3_done)||(!rd4_done)||(!rd5_done)||(!rd6_done)||(!rd7_done)||(!rd8_done)))?1'b1:1'b0;        
  assign app_wdf_wren =(((cstate == WR1 ||cstate == WR2 ||cstate == WR3 ||cstate == WR4 ||cstate == WR5 ||cstate == WR6 ||cstate == WR7 ||cstate == WR8) && app_wdf_rdy == 1'b1&&app_rdy == 1'b1)
  &&((!wr1_done)||(!wr2_done)||(!wr3_done)||(!wr4_done)||(!wr5_done)||(!wr6_done)||(!wr7_done)||(!wr8_done)))?1'b1:1'b0;
  
  always@(posedge ui_clk or negedge ui_clk_sync_rst)begin
     if(ui_clk_sync_rst == 1'b1)
            cstate <= IDLE;
     else
            cstate <= nstate; 
  end  
  
   always @(*) begin
          nstate = IDLE;
          case(cstate)
            IDLE:begin
              if(init_calib_complete == 1'b1)
                nstate = WR1;
              else
                nstate = IDLE;
            end
            WR1:begin
              if(wr1_done == 1'b1)
                nstate = WR2; 
              else
                nstate = WR1; 
            end
            WR2:begin
              if(wr2_done == 1'b1)
                nstate = WR3; 
              else
                nstate = WR2; 
            end
            WR3:begin
              if(wr3_done == 1'b1)
                nstate = WR4; 
              else
                nstate = WR3; 
            end
            WR4:begin
              if(wr4_done == 1'b1)
                nstate = WR5; 
              else
                nstate = WR4; 
            end
            WR5:begin
              if(wr5_done == 1'b1)
                nstate = WR6; 
              else
                nstate = WR5; 
            end
            WR6:begin
              if(wr6_done == 1'b1)
                nstate = WR7; 
              else
                nstate = WR6; 
            end
            WR7:begin
              if(wr7_done == 1'b1)
                nstate = WR8; 
              else
                nstate = WR7; 
            end
            WR8:begin
              if(wr8_done == 1'b1)
                nstate = RD1; 
              else
                nstate = WR8; 
            end
            RD1:begin
              if(rd1_done == 1'b1)
                nstate = RD2; 
              else
                nstate = RD1; 
             end
             RD2:begin
               if(rd2_done == 1'b1)
                 nstate = RD3; 
               else
                 nstate = RD2; 
             end
             RD3:begin
                if(rd3_done == 1'b1)
                  nstate = RD4; 
                else
                  nstate = RD3; 
             end
             RD4:begin
                if(rd4_done == 1'b1)
                  nstate = RD5; 
                else
                  nstate = RD4; 
             end
             RD5:begin
                if(rd5_done == 1'b1)
                  nstate = RD6; 
                else
                  nstate = RD5; 
             end
             RD6:begin
                if(rd6_done == 1'b1)
                  nstate = RD7; 
                else
                  nstate = RD6; 
             end
             RD7:begin
                if(rd7_done == 1'b1)
                  nstate = RD8; 
                else
                  nstate = RD7; 
             end
             RD8:begin
                if(rd8_done == 1'b1)
                  nstate = DONE; 
                else
                  nstate = RD8; 
             end
             DONE:begin
                nstate = WR1; 
             end
          endcase
        end
        
 always @(posedge ui_clk or posedge ui_clk_sync_rst) begin
                 if(ui_clk_sync_rst == 1'b1) begin
                   app_cmd <= `CMD_WR;
                   cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                   cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7;                       
                   bank <= 3'b000;
                   addr <=25'b0;
                 end
                 else
                   case(cstate)
                     WR1:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b000;
                       if(wr1_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7;     
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8;  
                       end
                     end
                     WR2:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b001;
                      if(wr2_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8;  
                       end
                     end
                     WR3:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b010;
                       if(wr3_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8; 
                       end
                     end
                     WR4:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b011;
                       if(wr4_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8; 
                       end
                     end   
                     WR5:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b100;
                       if(wr5_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8; 
                       end
                     end 
                     WR6:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b101;
                      if(wr6_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8; 
                       end
                     end 
                     WR7:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b110;
                      if(wr7_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8; 
                       end
                     end  
                     WR8:begin
                       app_cmd <= `CMD_WR;
                       bank <= 3'b111;
                       if(wr8_done == 1'b1) begin
                         addr <=25'b0;
                         cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                         cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                       end
                       else if(app_wdf_rdy == 1'b1&&app_rdy == 1'b1) begin
                         addr <= addr +8;
                         cout16_1 <= cout16_1+1; cout16_2 <= cout16_2+1; cout16_3 <= cout16_3+1; cout16_4 <= cout16_4+1;
                         cout16_5 <= cout16_5+1; cout16_6 <= cout16_6+1; cout16_7 <= cout16_7+1; cout16_8 <= cout16_8+1;  
                       end
                       else begin
                         addr <= addr;
                         cout16_1 <= cout16_1; cout16_2 <= cout16_2; cout16_3 <= cout16_3; cout16_4 <= cout16_4;
                         cout16_5 <= cout16_5; cout16_6 <= cout16_6; cout16_7 <= cout16_7; cout16_8 <= cout16_8; 
                       end
                     end     
                     RD1:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b000;
                       if(rd1_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     RD2:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b001;
                       if(rd2_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     RD3:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b010;
                       if(rd3_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     RD4:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b011;
                       if(rd4_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     RD5:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b100;
                       if(rd5_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     RD6:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b101;
                       if(rd6_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     RD7:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b110;
                       if(rd7_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     RD8:begin
                       app_cmd <= `CMD_RD;
                       bank <= 3'b111;
                       if(rd8_done == 1'b1) begin
                         addr <= 25'b0;
                       end
                       else if(app_rdy == 1'b1)begin
                          addr <= addr+8;
                       end
                       else begin
                         addr <= addr;
                       end
                     end
                     DONE:begin
                       bank <= 3'b000;
                       addr <=25'b0;
                       app_cmd <= `CMD_WR;
                       cout16_1 <= 16'd0; cout16_2 <= 16'd1; cout16_3 <= 16'd2; cout16_4 <= 16'd3;
                       cout16_5 <= 16'd4; cout16_6 <= 16'd5; cout16_7 <= 16'd6; cout16_8 <= 16'd7; 
                     end
                   endcase
               end

仿真测试

    在用modelsim做软仿的时候需要注意,testbench最好用官方给的代码,或者就在官方生成的项目上直接改example_top.自己写testbench很容易出错.一开始我是自己写的tesetbench做仿真,测试时总是有问题,后来才发现要用官方生成的testbench做仿真,才不会出错.

modelsim仿真结果如下:

DDR3读写仿真结果:
DDR3读写仿真结果
读操作
读操作
写操作
写操作

存在问题

    app_rdy和app_rd_data_valid是MIG控制核User Interface上的输出信号,我还不太清楚这两个信号什么时候置位,什么时候复位?到底是哪些因素影响了这两个信号的置位与复位?如果有看到这里的大神可以在评论区里帮忙解答一下~~

不聪明的阿哲
关注
  • 9
    点赞
  • 踩
  • 36
    收藏
    觉得还不错? 一键收藏
  • 1
    评论
专栏目录
FPGA读写DDR3
csdnqiang的博客
08-18 1万+
DDR3是一种内存规格，它是SDRAM家族的内存产品。DDR3之前的产品有DDR和DDR2。DDR（Double Data Rate）是双倍速率同步动态随机存储器，严格的说DDR应该叫DDR SDRAM。DDR2是DDR产品的升级产品，它是四倍速率同步动态随机存储器。DDR3在DDR2的基础上实现了更高的性能（增加到八倍）和更低的电压。 DDR内部结构框图如下所示： 如上图所示： 标号1：逻辑控制单元，用于输入命令解析和模式控制等。 标号2：行地址选通单元。 标号3：内部存储阵列，上图中分为8个bank。
基于紫光同创 FPGA 的 DDR3 读写实验
ChinaRyan666（蔡杰涛）的博客
10-15 3084
超级详细的3w字讲解！基于国产紫光同创平台！手撕DDR3读写~~
基于Xilinx FPGA的DDR3读写控制模块（包含整个工程）
07-05
基于Xilinx FPGA的DDR3控制器读写程序，此程序已经用于实际的项目中，读写控制很稳定。上传的是一个实际的DDR3工程，开发环境为Vivado 2017.4
FPGA（XILINX） DDR3 内存条 读写测试 仿真通过 （VIVADO 2015.2）
05-10
FPGA（XILINX） DDR3 内存条 读写测试 仿真通过 （VIVADO 2015.2）
xilinx fpga ddr3数据读写工程
09-17
该资源为ddr3数据读写代码工程，由vivado2018.2编写。低版本的软件请参考附带的教程，自行配置ip核。开发板为ax7035，芯片为xc7a35tfgg484，ddr3芯片为16bit位宽，直接上板使用，其他芯片需更改相关输入输出管脚。module文件代码量少，适合初学者了解ddr3的读写操作。
FPGA的a_7系列芯片对ddr3的控制
Headogerz的博客
09-24 4505
1.原理图——————这次设计的数据流是产生数据的模块是image-ctrl模块、ddr3控制模块、hdmi-buffer、vga-ctrl模块、以及hdmi转换模块。                该模块的有2个操作始终，其中vga_clk 65M是用来产生数据的，ui_clk为ddr3控制模块的写入数据与地址的时钟，跨时钟域数据传输将32bit的图像数据转换为128bit的数据。rd_e...
基于Xilinx FPGA的多通道DDR4读写控制模块（包含整个工程）
04-08
在本项目中，我们主要探讨的是如何在Xilinx FPGA中设计并实现一个基于AXI接口的多通道DDR4读写控制模块。这个工程的核心目标是创建一个能够支持四个独立读写通道的控制器，且通道数量可以通过参数进行配置，以适应...
XILINX的DDR3读写控制器
04-15
在标题"XILINX的DDR3读写控制器"中，我们关注的是Xilinx公司提供的DDR3内存控制器，它是FPGA内部设计的一个重要部分。这个控制器负责管理与DDR3内存芯片之间的读写操作，确保数据的正确传输和时序的精确控制。 描述...
利用Xilinx FPGA进行DDR3读写控制总结(一)
wnazhe45的博客
12-14 9294
利用Xilinx FPGA进行DDR3读写控制总结DDR3芯片结构Xilinx FPGA DDR3芯片结构 Xilinx FPGA
DDR3 读写程序
01-20
ddr3的读写程序，通过仿真测试和硬件平台测试，用的是vivado和modelsim，测试通过！用xilinx的ip核，用户接口模块是自己写的！
xilinx_DDR3控制代码
12-01
xilinx_DDR3控制代码,xilinx工程
FPGA 读写测试DDR3
neufeifatonju的博客
08-21 2137
多年前发的老帖子，最近用到DDR3，翻出来还能用，保存一下。 最近简单调了一下KC705开发板上面的DDR3，型号是MT8JTF12864HZ-1G6；有时候加载程序后，发现读出数据不是写进去的，在这将我的操作思路说下，有弄过的说说哪块有问题：1.ip核的sys_clk_i给400M时钟，clk_ref_i给200M时钟；app_wdf_mask全为0；app_sr_req,app_ref_req,app_zq_req接pull_down; 2.等初始化完成后(即init_calib_complet.
【fpga】ddr3
weixin_43778388的博客
12-05 5233
转载 1、前言         DDR3 SDRAM 简称 DDR3，是当今较为常见的一种储存器，在计算机及嵌入式产品中得到广泛应用， 特别是应用在涉及到大量数据交互的场合，比如电脑的内存条。DDR3的时序相当复杂，对DDR3 的读写操作大都借助 IP 核来完成。 2、MIG DDR3 IP核的介绍  &nbs
FPGA 20个例程篇：9.DDR3内存颗粒初始化写入并通过RS232读取（上）
wandou0511的博客
07-23 5381
在做嵌入式开发过程中“内存”仿佛是无处不在。DDR3颗粒作为当前较为常见的一种储存器，在计算机和嵌入式产品中得到广泛应用，尤其是在涉及到大数据量交互的场合，在FPGA领域比如视频加速处理、AD高速采集、PCIE上位机开发、SFP万兆光口传输等，几乎都能看到DDR3的身影，XILINX也为用户提供了MIG IP核方便实现对DDR3颗粒数据读写的二次开发，但市面上却鲜有不错的教程能快速带领大家入门上手，所以在这一章中笔者选取了两个经典的例程，通过它们就可以很好地去掌握MIG IP核的使用技巧。 DDR
基于fpga对ddr3的读写控制
热门推荐
Headogerz的博客
09-10 2万+
1.很多情况下，fpga的内部ip ram的存储量较小，所以需要外挂容量大的芯片。内部的芯片ram称为静态ram，其读写简单，速率中等，缺点就是存储空间较小。spartan—6芯片的最小单元为9k；充电刷新保持数据的额sdram称为动态ram，其容量大，缺点就是高功耗，管脚多，操作时许复杂，占用面积大。无论是静态还是动态ram都是一种易失性器件。 2.当前比较常用的是ddr3，有关ddr3的介绍...
FPGA通过MIG IP读写DDR3
weixin_44678052的博客
08-14 1097
本期将接收如何驱动DDR3存储器，当然不会像SDRAM那样，自己手写驱动；而是借助Vivado提供的MIG IP来完成这项工作。但是建议在学习DDR3之前，可以学习一下且写一下SDRAM的驱动，因为它们的涉及到的存储原理和框架一样，只不过DDR3在其基础上增加了一些功能和特性而变得复杂了起来，学会了SDRAM可以约等于学会了DDR3，是不是很nice。IP核的创建就不作过多的介绍了，点点点就可以，在关键的位置注意一下就可以了(与硬件电路是否一致)。
利用Xilinx FPGA进行DDR3读写控制总结(二)
wnazhe45的博客
12-15 2334
MIG控制器概述   MIG IP核的结构如上图所示,可以看出MIG控制核主要有三个部分组成:User Interface Block, Memory Controller, Physical Layer. 而我们在利用MIG控制核对DDR3读写时需要了解并做好逻辑控制的主要是User Interface.   User Interface中各信号的定义以及时序在Xilinx 的MIG用户手册(UG586)上有非常详细的描述,这里就不介绍了,因为在使用一个IP核之前还是要先学会看用户手册的.   对Use
FPGA-基于AXI4接口的DDR3读写顶层模块
最新发布
qq_45248833的博客
11-08 1676
AXI4（Advancede Xtensible Interface 4）是一种高性能、高带宽的总线接口协议，用于在系统级芯片设计中连接不同的IP核（Intellectual Property）或模块。它是由ARM公司开发的，被广泛应用于各种SoC（System-on-Chip）设计中。AXI4接口协议定义了一组规范，用于描述数据传输、地址传输、控制信号和时序等方面的要求。它提供了一种灵活的、可扩展的接口，支持高性能和低功耗的系统设计。灵活性：AXI4接口支持多种传输模式，包括单个传输、突发传输和流传输。
xilinx fpga的ddr3读写
06-28
### 回答1： Xilinx FPGA的DDR3读写是指使用FPGA芯片控制DDR3存储器进行读写操作。DDR3是一种高速存储器，具有较高的带宽和容量，适用于需要大量数据处理的应用场景。在使用Xilinx FPGA控制DDR3存储器时，需要进行时序设计和控制信号的生成，以确保数据的正确读写和传输。同时，还需要考虑存储器的时序参数和信号电平等因素，以保证系统的稳定性和可靠性。 ### 回答2： DDR3双倍数据速率（Double Data Rate 3）是一种常用的动态随机存取存储器，用于存储大量数据。在Xilinx FPGA中，使用DDR3存储器可以提高数据存储和读写速度，从而提高FPGA的性能表现。 首先，使用DDR3存储器需要进行初始化设置，包括设置读取延迟、写入延迟、数据宽度、读取优先级、写入优先级等参数。在初始化设置完成后，就可以开始进行DDR3的读写操作。 对于DDR3的写操作，需要将要写入的数据存储到FPGA的内部缓存器中，然后通过写入请求延迟周期，将缓存器中的数据写入到DDR3存储器中。另外，写入数据时需要注意写入地址的对齐和写入数据的宽度限制。 对于DDR3的读操作，需要先发送读取请求延迟周期，然后等待存储器返回数据，将返回的数据存储到FPGA的内部缓存器中，最后进行下一步操作。在进行读操作时，需要注意读取地址的对齐和读取数据的宽度限制。 需要注意的是，DDR3存储器操作的速度与时序非常重要，对于每个DDR3存储器，都有自己的特定时序，需要按照特定时序进行读写操作。此外，为了保证DDR3存储器的正常工作，需要进行信号干扰和噪声等方面的优化，并进行时序的校准。 总之，Xilinx FPGA的DDR3读写操作是一项复杂的任务，需要仔细的设置时序和参数，并进行干扰和噪声的优化，才能保证存储器的稳定性和可靠性。 ### 回答3： Xilinx FPGA的DDR3读写是指通过FPGA控制器实现FPGA与DDR3内存交互的过程。DDR3内存是一种高速存储器，比之前的DDR2和DDR1速度更快，容量更大，增强了系统的稳定性和响应速度。在FPGA应用中，使用DDR3内存可以提高系统的数据处理速度，同时，实现高性能和低延迟操作。 在Xilinx FPGA的DDR3读写过程中，需要几个关键的元素来实现这个过程。其中，主要包括控制器，时钟和DDR PHY。控制器负责与DDR3内存通信，时钟用于同步在通信过程中产生的信号，DDR PHY负责处理数据在FPGA和DDR3之间的传输。此外，还需要使用IP核来设置DDR3控制器中的时序参数和其他必要的参数。 在实现DDR3读写时，需要注意几个关键的过程。首先，需要在设计时对时序进行精确的计算。其次，需要合理使用DDR3的时序，来优化数据传输。然后，需要使用FPGA内部的PHY来配置芯片和DDR3设备之间的数据传输通道。最后，需要使用IP核来调整DDR3控制器的电路参数，以确保数据在FPGA和DDR3内存之间的传输被优化。 综上所述，Xilinx FPGA的DDR3读写是一项基于FPGA的高速数据传输技术，通过控制器、时钟和DDR PHY与DDR3内存进行交互。控制DDR3读写的关键是准确计算时序、优化传输通道，以及调整相关参数。它可以大大提高系统的数据处理能力，由于速度快、容量大等优点而被广泛应用。
评论 1
添加红包

请填写红包祝福语或标题

个

红包个数最小为10个

元

红包金额最低5元

当前余额3.43元 前往充值 >
需支付：10.00元
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付元
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明：

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。

余额充值