ModelSim中编译synplify库

1. 退出仿真：quit -sim
2. 切换目录：cd Y:/Program/LiberoSoCv11/SynplifyPro/lib/vhdl_sim/
3. 建立新库：vlib synplify
4. 映射路径：vmap synplify Y:/Program/LiberoSoCv11/SynplifyPro/lib/vhdl_sim/synplify
5. 编译文件：vcom -2008 -explicit  -work synplify "synplify.vhd"
6. 编译文件：vcom -2008 -explicit  -work synplify "../vhdl/synattr.vhd"
7. 开始仿真：vsim ... -L synplify -lib work work.tb_....
8. 代码头部：library synplify;use synplify.attributes.all;