Gate Level Modeling Part-III (of Verilog HDL)

		Gate and Switch delays //门时延和开关时延
		In real circuits, logic gates have delays associated with them. Verilog provides the mechanism to associate delays with gates. 在真正的电路中，逻辑电路都有一定的时延。Verilog HDL提供了一种带时延的门的机制。
		Rise, Fall and Turn-off delays. //上升沿时延，下降沿时延、关闭时延 Minimal, Typical, and Maximum delays. //最小时延、典型时延、最大时延
		In Verilog delays can be introduced with #'num' as in the examples below, where # is a special character to introduce delay, and 'num' is the number of ticks simulator should delay current statement execution. 在Verilog中, 如下面的例子中，可以通过#num（#数字）进行引入时延，这里#是一个用来引入时延的特殊字符。num 这个数字是仿真器将要延迟的仿真器的num个时间单位再执行当前语句。
		#1 a = b : Delay by 1, i.e. execute after 1 tick  //延迟一个时间单位执行 a=b; #2 not (a,b) : Delay by 2 all assignments made to a = ！b. //延迟2个时间单位 a = ！b;
		Real transistors have resolution delays between the input and output. This is modeled in Verilog by specifying one or more delays for the rise, fall, turn-on and turn off time seperated by commas. 真正的三极管在输入和输出有着决议延迟。这个在Verilog中可以为上升时延，下降时延、关闭时延 (用逗号分隔)指派1到2个时延单位。
		Syntax: keyword #(delay{s}) unique_name (node specifications); //指派时延的格式，此处的delay默认的typical时延
		Switch element Number Of Delays Specified delays Switch 1 Rise, fall and turn-off times of equal length 2 Rise and fall times 3 Rise, fall and turn off (r)tranif0, (r)tranif1 1 both turn on and turn off 2 turn on, turn off (r)tran 0 None allowed  //不允许有时延
		Rise Delay //上升沿时延
		The rise delay is associated with a gate output transition to 1 from another value (0, x, z). 上升沿时延，与门的输入从0，x, z,变换到1的转变过程, 即产生上升沿的过程。 即gate output 从非1 变换到1的状态。
		Fall Delay //下降沿
		The fall delay is associated with a gate output transition to 0 from another value (1, x, z). 下降沿时延， 产生下降沿的时延，即门的输出从1，x，z，变换到0， 即gate ouput 从非0，变换到0.
		Turn-off Delay //关闭时延
		The Turn-off delay is associated with a gate output transition to z from another value (0, 1, x). 关闭时延，即gate output从非Z变换到z的转换过程。
		Min Value //最小时延
		The min value is the minimum delay value that the gate is expected to have. 最小时延，gate完成变换时期望的最小需求时间。
		Typ Value ：typical value 时延典型值
		The typ value is the typical delay value that the gate is expected to have. 时延的典型值，是指gate所要求的典型值。
		Max Value //时延的最大值
		The max value is the maximum delay value that the gate is expected to have. 时延最大值，gate所预判的最大值
		Example //举例
		Below are some examples to show the usage of delays. 下面是一些时延使用的例子。
		Example - Single Delay //单时延 = 上升沿时延= 下降沿时延
		1 module buf_gate (); 2 reg in; 3 wire out; 4 5 buf #(5) (out,in); 6 7 initial begin 8 $monitor ("Time = %g in = %b out=%b", $time, in, out); 9 in = 0; 10 #10 in = 1; 11 #10 in = 0; 12 #10 $finish; 13 end 14 15 endmodule You could download file buf_gate.v here
		Time = 0 in = 0 out=x Time = 5 in = 0 out=0 Time = 10 in = 1 out=0 Time = 15 in = 1 out=1 Time = 20 in = 0 out=1 Time = 25 in = 0 out=0
		Example - Two Delays // 双时延举例 (上升沿时延，下降沿时延)。
		1 module buf_gate1 (); 2 reg in; 3 wire out; 4 5 buf #(2,3) (out,in); 6 7 initial begin 8 $monitor ("Time = %g in = %b out=%b", $time, in, out); 9 in = 0; 10 #10 in = 1; 11 #10 in = 0; 12 #10 $finish; 13 end 14 15 endmodule You could download file buf_gate1.v here
		Time = 0 in = 0 out=x Time = 3 in = 0 out=0 Time = 10 in = 1 out=0 Time = 12 in = 1 out=1 Time = 20 in = 0 out=1 Time = 23 in = 0 out=0
		Example - All Delays
		1 module delay(); 2 reg in; 3 wire rise_delay, fall_delay, all_delay; 4 5 initial begin 6 $monitor ( 7 "Time=%g in=%b rise_delay=%b fall_delay=%b all_delay=%b", 8 $time, in, rise_delay, fall_delay, all_delay); 9 in = 0; 10 #10 in = 1; 11 #10 in = 0; 12 #20 $finish; 13 end 14 15 buf #(1,0)U_rise (rise_delay,in); 16 buf #(0,1)U_fall (fall_delay,in); 17 buf #1 U_all (all_delay,in); 18 19 endmodule You could download file delay.v here
		Time = 0 in = 0 rise_delay = 0 fall_delay = x all_delay = x Time = 1 in = 0 rise_delay = 0 fall_delay = 0 all_delay = 0 Time = 10 in = 1 rise_delay = 0 fall_delay = 1 all_delay = 0 Time = 11 in = 1 rise_delay = 1 fall_delay = 1 all_delay = 1 Time = 20 in = 0 rise_delay = 0 fall_delay = 1 all_delay = 1 Time = 21 in = 0 rise_delay = 0 fall_delay = 0 all_delay = 0
		Example - Complex Example 复杂举例：时延的实例
		1 module delay_example(); 2 3 wire out1,out2,out3,out4,out5,out6; 4 reg b,c; 5 6 // Delay for all transitions //所有三极管的时延 7 or #5 u_or (out1,b,c); 8 // Rise and fall delay //（Rise_delay, fall_delay) 9 and #(1,2) u_and (out2,b,c); 10 // Rise, fall and turn off delay // (rise_delay, fall_delay, turn_off_delay) 11 nor #(1,2,3) u_nor (out3,b,c); 12 //One Delay, min, typ and max //上升沿时延（min：typical： max） 13 nand #(1:2:3) u_nand (out4,b,c); 14 //Two delays, min,typ and max 15 buf #(1:4:8,4:5:6) u_buf (out5,b); 16 //Three delays, min, typ, and max 17 notif1 #(1:2:3,4:5:6,7:8:9) u_notif1 (out6,b,c); 18 19 //Testbench code 20 initial begin 21 $monitor ( 22 "Time=%g b=%b c=%b out1=%b out2=%b out3=%b out4=%b out5=%b out6=%b", 23 $time, b, c , out1, out2, out3, out4, out5, out6); 24 b = 0; 25 c = 0; 26 #10 b = 1; 27 #10 c = 1; 28 #10 b = 0; 29 #10 $finish; 30 end 31 32 endmodule You could download file delay_example.v  here
		关于Verilog中的时延的总结： 时延分为上升沿时延，下降沿时延、关闭时延，     Verilog HDL 通过 primitiveName #(<上升沿时延>，<下降沿时延> ，<关闭时延>) (参数表）； 而每种时延又有三种可能的取值<时延> := <min : typ : max>; 因此，通过它们组合，指派器件的内部时延有多种方式，
		Time = 0 b = 0 c=0 out1=x out2=x out3=x out4=x out5=x out6=x Time = 1 b = 0 c=0 out1=x out2=x out3=1 out4=x out5=x out6=x Time = 2 b = 0 c=0 out1=x out2=0 out3=1 out4=1 out5=x out6=z Time = 5 b = 0 c=0 out1=0 out2=0 out3=1 out4=1 out5=0 out6=z Time = 8 b = 0 c=0 out1=0 out2=0 out3=1 out4=1 out5=0 out6=z Time = 10 b = 1 c=0 out1=0 out2=0 out3=1 out4=1 out5=0 out6=z Time = 12 b = 1 c=0 out1=0 out2=0 out3=0 out4=1 out5=0 out6=z Time = 14 b = 1 c=0 out1=0 out2=0 out3=0 out4=1 out5=1 out6=z Time = 15 b = 1 c=0 out1=1 out2=0 out3=0 out4=1 out5=1 out6=z Time = 20 b = 1 c=1 out1=1 out2=0 out3=0 out4=1 out5=1 out6=z Time = 21 b = 1 c=1 out1=1 out2=1 out3=0 out4=1 out5=1 out6=z Time = 22 b = 1 c=1 out1=1 out2=1 out3=0 out4=0 out5=1 out6=z Time = 25 b = 1 c=1 out1=1 out2=1 out3=0 out4=0 out5=1 out6=0 Time = 30 b = 0 c=1 out1=1 out2=1 out3=0 out4=0 out5=1 out6=0 Time = 32 b = 0 c=1 out1=1 out2=0 out3=0 out4=1 out5=1 out6=1 Time = 35 b = 0 c=1 out1=1 out2=0 out3=0 out4=1 out5=0 out6=1
		N-Input Primitives  //N输入原语
		The and, nand, or, nor, xor, and xnor primitives have one output and any number of inputs  and, nand, or, nor, nor, xor, xnor这些原语共同点是只有一个输出，当可以有任意个输入。
		The single output is the first terminal. //第一个端口是唯一的输出 All other terminals are inputs. //其他所以的端口是输入。
		Examples //举例
		1 module n_in_primitive(); 2 3 wire out1,out2,out3; 4 reg in1,in2,in3,in4; 5 6 // Two input AND gate 7 and u_and1 (out1, in1, in2); 8 // four input AND gate 9 and u_and2 (out2, in1, in2, in3, in4); 10 // three input XNOR gate 11 xnor u_xnor1 (out3, in1, in2, in3); 12 13 //Testbench Code 14 initial begin 15 $monitor ( 16 "in1 = %b in2 = %b in3 = %b in4 = %b out1 = %b out2 = %b out3 = %b", 17 in1, in2, in3, in4, out1, out2, out3); 18 in1 = 0; 19 in2 = 0; 20 in3 = 0; 21 in4 = 0; 22 #1 in1 = 1; 23 #1 in2 = 1; 24 #1 in3 = 1; 25 #1 in4 = 1; 26 #1 $finish; 27 end 28 29 endmodule You could download file n_in_primitive.v here
		in1 = 0 in2 = 0 in3 = 0 in4 = 0 out1 = 0 out2 = 0 out3 = 1 in1 = 1 in2 = 0 in3 = 0 in4 = 0 out1 = 0 out2 = 0 out3 = 0 in1 = 1 in2 = 1 in3 = 0 in4 = 0 out1 = 1 out2 = 0 out3 = 1 in1 = 1 in2 = 1 in3 = 1 in4 = 0 out1 = 1 out2 = 0 out3 = 0 in1 = 1 in2 = 1 in3 = 1 in4 = 1 out1 = 1 out2 = 1 out3 = 0
		N-Output Primitives //n 输出的原语
		The buf and not primitives have any number of outputs and one input buf, not这两个原语可以有任意多个输出，但只有唯一的一个输入。
		The outputs are the first terminals listed. //除了最后一个端口外都是输出 The last terminal is the single input. //最后一个端口是输入
		Examples 举例
		1 module n_out_primitive(); 2 3 wire out,out_0,out_1,out_2,out_3,out_a,out_b,out_c; 4 wire in; 5 6 // one output Buffer gate 7 buf u_buf0 (out,in); 8 // four output Buffer gate 9 buf u_buf1 (out_0, out_1, out_2, out_3, in); 10 // three output Invertor gate 11 not u_not0 (out_a, out_b, out_c, in); 12 13 endmodule You could download file n_out_primitive.v here
		总结：无论是n-input原语还是n-out原语，原语的端口列表都是先输出，后输入的顺序，区别是n-input原语只有一个输出，而n-output只有一个输入。

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