User Defined Primitives Part-III (of Verilog HDL)

		Level Sensitive Sequential UDP //电平触发的时序udp
		Level-sensitive sequential behavior is represented in the same way as combinational behavior, except that the output is declared to be of type reg, and there is an additional field in each table entry. This new field represents the current state of the UDP. 电平触发的时序逻辑 udp的行为除了输出端口要声明为reg外的表示方法是一样的。此外的一点区别是真值表中的每一行有一个附加域，这个新的域表示UDP的当前状态。
		The output is declared as reg to indicate that there is an internal state. The output value of the UDP is always the same as the internal state. 输出声明为reg，来表明其有个内部状态。udp的输出值总是和其内部值是一致的。 A field for the current state has been added. This field is separated by colons from the inputs and the output. 真值表中每个行中添加了一个当前状态域（current state）。这个域与input 和output用：（colon）分隔，也就是说在input和output之间。 则其真值表中的一行是： input field(s): current state field : output field
		Sequential UDPs have an additional field inserted between the input fields and the output field, compared to combinational UDP. This additional field represents the current state of the UDP and is considered equivalent to the current output value. It is delimited by colons. 与组合逻辑电路的udp相比， 时序逻辑的udp有一个额外的域（current state）插入在input域和输出域之间。这个附加的域表明udp的当前状态，也是当前的输出。 它们用colon（：）分隔。
		1 primitive udp_seq (.....); 2 3 table 4 0 0 0 : 0 : 0; 5 ... 6 endtable 7 8 endprimitive You could download file udp_seq.v here
		Example  //举例
		1 primitive udp_latch(q, clk, d) ; 2 output q; 3 input clk, d; 4 5 reg q; 6 7 table 8 //clk d q q+ 9 0 1 : ? : 1 ; 10 0 0 : ? : 0 ; 11 1 ? : ? : - ; 12 endtable 13 14 endprimitive You could download file udp_latch.v here
		Edge-Sensitive UDPs //边沿触发的UDP
		In level-sensitive behavior, the values of the inputs and the current state are sufficient to determine the output value. Edge-sensitive behavior differs in that changes in the output are triggered by specific transitions of the inputs. 在电平触发的时序逻辑电路UDP中，输入和当前的状态值能充分的决定其输出值。 而边沿触发的udp不同点是输出的变化，由 其中某一个具体的输入的变化决定。
		As in the combinational and the level-sensitive entries, a ? implies iteration of the entry over the values 0, 1, and x. A dash (-) in the output column indicates no value change. 和组合逻辑的udp和电平触发的udp中的真值表的实体一样， ？代表这0， 1， x三个值中的一个。 输出列中-（dash）表明值没有变化。
		All unspecified transitions default to the output value x. Thus, in the previous example, transition of clock from 0 to x with data equal to 0 and current state equal to 1 result in the output q going to x. 所有的未指派的组合情形的输出的默认值是x。因此，在上一个例子中，如果clock的值从0变为x ，d= 0，当前的状态为1，将导致q的输出为x，因为真值表中的没有相关的line，则对于真值表中不存在的表记录，默认的输出值为x。
		All transitions that should not affect the output must be explicitly specified. Otherwise, they will cause the value of the output to change to x. If the UDP is sensitive to edges of any input, the desired output state must be specified for all edges of all inputs. 那些不能影响输出的状态转换，必须被显示指派。否则，它们将造成输出值变为x。 如果udp的是所有输入的所有边沿触发的，则必须为所有的边沿指派输入。
		Example //例子
		1 primitive udp_sequential(q, clk, d); 2 output q; 3 input clk, d; 4 5 reg q; 6 7 table 8 // obtain output on rising edge of clk 9 // clk d q q+ 10 (01) 0 : ? : 0 ; 11 (01) 1 : ? : 1 ; 12 (0?) 1 : 1 : 1 ; 13 (0?) 0 : 0 : 0 ; 14 // ignore negative edge of clk 15 (?0) ? : ? : - ; 16 // ignore d changes on steady clk 17 ? (??) : ? : - ; 18 endtable 19 20 endprimitive You could download file udp_sequential.v here
		Example UDP with initial //带初始化的udp
		1 primitive udp_sequential_initial(q, clk, d); 2 output q; 3 input clk, d; 4 5 reg q; 6 7 initial begin 8 q = 0; 9 end 10 11 table 12 // obtain output on rising edge of clk 13 // clk d q q+ 14 (01) 0 : ? : 0 ; 15 (01) 1 : ? : 1 ; 16 (0?) 1 : 1 : 1 ; 17 (0?) 0 : 0 : 0 ; 18 // ignore negative edge of clk 19 (?0) ? : ? : - ; 20 // ignore d changes on steady clk 21 ? (??) : ? : - ; 22 endtable 23 24 endprimitive You could download file udp_sequential_initial.v here

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