Introduction //简介 Before you Start Example - Counter 计数器举例 Code for CounterTest PlanTest Cases Writing a TestBench //写测试基准程序 Test BenchTest Bench with Clock generatorTest Bench continues...Adding Reset LogicCode of reset logicAdding test case logic Test Case 1 - Asserting/ De-asserting resetTest Case 2 - Assert/ De-assert enable after reset is applied.Test Case 3 - Assert/De-assert enable and reset randomly. Adding compare Logic the above original link: http://www.asic-world.com/verilog/art_testbench_writing.html