HDLBits 刷题之我的代码（全）—（Verification:Writing Testbenches）

#1

`timescale 1ps/1ps
module top_module ( );

	reg clk;
    initial begin
        clk = 'b0;
        forever 
            #5 clk = ~clk;
    end
 	dut dut1(.clk(clk));
endmodule

#2

`timescale 1ps/1ps
module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
		A = 0;
        #10
		A = 1;
        #10 
        A = 0;             
    end
    initial begin
        B = 0;
        #15
        B = 1;
        #25  
        B = 0;       
    end
endmodule

#3

`timescale 1ps/1ps
module top_module();
    reg [1:0]in;
    wire out;
	initial begin
        in = 0;
        #10
        in = 1;
        #10
        in = 2;
        #10
        in = 3;      
    end
    andgate u_andgate(
        .in(in),
        .out(out)
	);
endmodule

#4

`timescale 1ps/1ps
module top_module();
    
    reg [2:0]s;
    reg clk;
    reg in;
    wire out;
    initial begin
        clk = 0;
        forever
            #5 clk = ~clk;
    end
	initial begin
        in = 0;
        s = 2;
        #10
        in = 00;
        s = 6;
        #10
        in = 1;
        s = 2;
        #10
        in = 0; 
        s = 7;
        #10
        in = 1;
        s = 0;
        #30
        in = 0;
    end
	q7 u_q7(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out)
	);
endmodule

#5

`timescale 1ps/1ps
module top_module ();
	reg clk;
    reg reset;
    reg t;
    wire q;
    initial begin
        clk = 0;
        forever
            #5 clk = ~clk;
    end
	initial begin
        reset = 1;
        t = 0;
        #10
        reset = 0;
        t = 1;
        #20
        reset = 1;
        t = 0;
    end
	tff  u_tff (
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q)
	);    
endmodule