名称:基于FPGA的音乐播放器设计VHDL代码ISE basys2开发板(文末获取)
软件:ISE
语言:VHDL
代码功能:
功能:①预存四首以上的乐曲(正能量,主旋律),将乐曲以ROM IP核的方式存储。
②可手动控制播放、暂停、切换到“上一首或“下一首。
③白行配合加入8位LED灯、4位七段数码管的显示效果,按照乐由播放的进度用数码管显示简谱
本代码已在basys2开发板验证,basys2开发板如下,其他开发板可以修改管脚适配:
1. 工程文件
2. Testbench
3. 仿真图
3.1 整体仿真
3.2 key_jitter模块
3.3 music_ctrl模块
3.4 musicdec模块
3.5 display模块
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; --数码管显示模块 ENTITY display IS PORT ( clk : IN STD_LOGIC; music_num : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--简谱 HEX0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--数码管-低亮 ); END display; ARCHITECTURE behavioral OF display IS BEGIN PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN CASE music_num IS--数字显示码 WHEN "00000000" => HEX0 <= "11000000"; WHEN "00000001" => HEX0 <= "11111001"; WHEN "00000010" => HEX0 <= "10100100"; WHEN "00000011" => HEX0 <= "10110000"; WHEN "00000100" => HEX0 <= "10011001"; WHEN "00000101" => HEX0 <= "10010010"; WHEN "00000110" => HEX0 <= "10000010"; WHEN "00000111" => HEX0 <= "11111000"; WHEN "00001000" => HEX0 <= "10000000"; WHEN "00001001" => HEX0 <= "10010000"; WHEN "00001010" => HEX0 <= "10001000"; WHEN "00001011" => HEX0 <= "10000011"; WHEN "00001100" => HEX0 <= "11000110"; WHEN "00001101" => HEX0 <= "10100001"; WHEN "00001110" => HEX0 <= "10000110"; WHEN "00001111" => HEX0 <= "10001110"; WHEN OTHERS => END CASE; END IF; END PROCESS; END behavioral;
源代码
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