verilog学习笔记：简单的数据选择器modelsim仿真

如图所示，画出框图，有sel、in_1、in_2三个输出入，sel为选通器、in为信号，sel为高电平时输出in_1,否则输出in_2;

利用if语句实现该过程，代码如下：

module mux2_1
(
    input  wire           [0:0]         in_1                       ,//输入信号1
    input  wire           [0:0]         in_2                       ,//输入信号2
    input  wire           [0:0]         sel                        ,//选通信号
    output reg            [0:0]         out                         //输出信号
);
    //out:输出信号
    always@(sel,in_1,in_2)
        if (sel==1'b1)
        begin
            out=in_1;
        end
        else 
        begin
            out=in_2;
        end
endmodule

 将代码导入quartusII进行编译成功，然后添加仿真代码：

`timescale 1ns/1ns
module tb_mux2_1 ();
    reg                                     in_1                       ;
    reg                                     in_2                       ;
    reg                                     sel                        ;
    wire                                    out                        ;
    initial begin
        in_1<=1'b0;
        in_2<=1'b0;
        sel<=1'b0;
    end
    always #10 in_1<={$random}%2;
    always #10 in_2<={$random}%2;
    always #10 sel<={$random}%2;
    initial begin
        $timeformat(-9,0,"ns",6);
        $monitor("@time %t:in_1=%b in_2=%b sel=%b out=%b",$time,in_1,in_2,sel,out);
    end
    mux2_1 mux2_1_inst
    (
        .in_1                              (in_1                     ),//输入信号1
        .in_2                              (in_2                     ),//输入信号2
        .sel                               (sel                      ),//选通信号
        .out                               (out                      ) //输出信号
    );
endmodule

利用modelsim仿真结果如下：

 文字仿真表达结果：

# run 1 us
# @time    0ns:in_1=0 in_2=0 sel=0 out=0
# @time   10ns:in_1=0 in_2=1 sel=1 out=0
# @time   20ns:in_1=1 in_2=1 sel=1 out=1
# @time   30ns:in_1=1 in_2=0 sel=1 out=1
# @time   60ns:in_1=0 in_2=1 sel=0 out=1
# @time   70ns:in_1=1 in_2=1 sel=0 out=1
# @time   80ns:in_1=1 in_2=0 sel=0 out=0
# @time   90ns:in_1=0 in_2=1 sel=0 out=1
# @time  100ns:in_1=1 in_2=1 sel=1 out=1
# @time  110ns:in_1=1 in_2=0 sel=0 out=0
# @time  120ns:in_1=0 in_2=0 sel=1 out=0
# @time  130ns:in_1=0 in_2=1 sel=1 out=0
# @time  140ns:in_1=1 in_2=1 sel=1 out=1
# @time  150ns:in_1=0 in_2=0 sel=1 out=0
# @time  160ns:in_1=1 in_2=1 sel=0 out=1
# @time  170ns:in_1=0 in_2=0 sel=0 out=0
# @time  180ns:in_1=0 in_2=1 sel=0 out=1
# @time  190ns:in_1=0 in_2=1 sel=1 out=0
# @time  200ns:in_1=0 in_2=0 sel=0 out=0
# @time  210ns:in_1=0 in_2=0 sel=1 out=0
# @time  220ns:in_1=1 in_2=1 sel=1 out=1
# @time  230ns:in_1=1 in_2=0 sel=0 out=0
# @time  240ns:in_1=1 in_2=1 sel=1 out=1
# @time  250ns:in_1=0 in_2=0 sel=1 out=0
# @time  260ns:in_1=1 in_2=0 sel=1 out=1
# @time  280ns:in_1=1 in_2=1 sel=0 out=1
# @time  300ns:in_1=0 in_2=0 sel=0 out=0
# @time  310ns:in_1=1 in_2=1 sel=0 out=1
# @time  320ns:in_1=0 in_2=1 sel=1 out=0
# @time  330ns:in_1=1 in_2=1 sel=1 out=1
# @time  340ns:in_1=0 in_2=1 sel=1 out=0
# @time  350ns:in_1=1 in_2=0 sel=0 out=0
# @time  360ns:in_1=0 in_2=0 sel=0 out=0
# @time  370ns:in_1=0 in_2=0 sel=1 out=0
# @time  380ns:in_1=1 in_2=1 sel=1 out=1
# @time  390ns:in_1=1 in_2=0 sel=1 out=1
# @time  400ns:in_1=1 in_2=0 sel=0 out=0
# @time  410ns:in_1=1 in_2=1 sel=0 out=1
# @time  420ns:in_1=1 in_2=1 sel=1 out=1
# @time  430ns:in_1=1 in_2=0 sel=0 out=0
# @time  440ns:in_1=0 in_2=1 sel=0 out=1
# @time  450ns:in_1=0 in_2=0 sel=1 out=0
# @time  460ns:in_1=1 in_2=0 sel=0 out=0
# @time  480ns:in_1=0 in_2=1 sel=0 out=1
# @time  500ns:in_1=1 in_2=1 sel=1 out=1
# @time  510ns:in_1=1 in_2=1 sel=0 out=1
# @time  520ns:in_1=0 in_2=0 sel=1 out=0
# @time  540ns:in_1=1 in_2=0 sel=0 out=0
# @time  550ns:in_1=0 in_2=1 sel=1 out=0
# @time  560ns:in_1=0 in_2=0 sel=0 out=0
# @time  570ns:in_1=1 in_2=1 sel=0 out=1
# @time  580ns:in_1=0 in_2=0 sel=1 out=0
# @time  600ns:in_1=0 in_2=0 sel=0 out=0
# @time  610ns:in_1=1 in_2=0 sel=1 out=1
# @time  620ns:in_1=1 in_2=0 sel=0 out=0
# @time  630ns:in_1=0 in_2=0 sel=1 out=0
# @time  640ns:in_1=0 in_2=0 sel=0 out=0
# @time  650ns:in_1=0 in_2=1 sel=1 out=0
# @time  660ns:in_1=1 in_2=0 sel=1 out=1
# @time  670ns:in_1=1 in_2=1 sel=0 out=1
# @time  680ns:in_1=0 in_2=1 sel=1 out=0
# @time  690ns:in_1=1 in_2=1 sel=1 out=1
# @time  700ns:in_1=0 in_2=1 sel=1 out=0
# @time  710ns:in_1=0 in_2=0 sel=0 out=0
# @time  720ns:in_1=0 in_2=1 sel=1 out=0
# @time  730ns:in_1=0 in_2=0 sel=1 out=0
# @time  770ns:in_1=1 in_2=1 sel=0 out=1
# @time  780ns:in_1=0 in_2=0 sel=1 out=0
# @time  800ns:in_1=0 in_2=0 sel=0 out=0
# @time  810ns:in_1=0 in_2=1 sel=0 out=1
# @time  820ns:in_1=0 in_2=0 sel=1 out=0
# @time  830ns:in_1=1 in_2=0 sel=1 out=1
# @time  840ns:in_1=1 in_2=1 sel=1 out=1
# @time  850ns:in_1=0 in_2=1 sel=1 out=0
# @time  860ns:in_1=1 in_2=0 sel=0 out=0
# @time  880ns:in_1=1 in_2=1 sel=0 out=1
# @time  890ns:in_1=0 in_2=1 sel=0 out=1
# @time  910ns:in_1=1 in_2=1 sel=0 out=1
# @time  920ns:in_1=1 in_2=0 sel=1 out=1
# @time  930ns:in_1=0 in_2=0 sel=1 out=0
# @time  940ns:in_1=0 in_2=0 sel=0 out=0
# @time  950ns:in_1=1 in_2=1 sel=1 out=1
# @time  960ns:in_1=1 in_2=1 sel=0 out=1
# @time  970ns:in_1=1 in_2=1 sel=1 out=1
# @time  980ns:in_1=0 in_2=0 sel=0 out=0
# Causality operation skipped due to absence of debug database file

分析结果可知仿真成功，结束。