Xtensa——Cache

Xtensa——Cache

小狼@http://blog.csdn.net/xiaolangyangyang

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1、Xtensa Cache基本参数

Xtensa系列Cache参数如下：
Cache Level：L1
ICache Size：32K（4-way）
DCache Size：32K（4-way）
Cache Line：128B

2、Cache接口函数

Global Cache Control Functions
全局控制操作应用于整个缓存。

         XTHAL_L2_SETUP(ram_paddr, ram_fraction, cache_fraction);
 int32_t xthal_L2_repartiton(uint32_t ram, uint32_t cache);
uint32_t xthal_get_cacheattr(void);             // read CACHEATTR register
    void xthal_set_cacheattr(uint32_t);         // write CACHEATTR register
uint32_t xthal_get_icacheattr(void);            // read icache CACHEATTR equiv
    void xthal_set_icacheattr(uint32_t);        // write "
uint32_t xthal_get_dcacheattr(void);            // read dcache CACHEATTR equiv
    void xthal_set_dcacheattr(uint32_t);        // write "
    void xthal_icache_sync(void);               // sync icache and memory
    void xthal_dcache_sync(void);               // sync dcache and memory
uint32_t xthal_icache_get_ways(void);           // read enabled icache ways
    void xthal_icache_set_ways(uint32_t);       // write "
uint32_t xthal_dcache_get_ways(void);           // read enabled dcache ways
    void xthal_dcache_set_ways(uint32_t);       // write "
    void xthal_icache_all_invalidate(void);     // invalidate the icache
    void xthal_dcache_all_invalidate(void);     // invalidate the dcache
    void xthal_dcache_L1_all_invalidate(void);
    void xthal_dcache_all_writeback(void);      // write-back dcache to memory
    void xthal_dcache_all_writeback_inv(void);  // write dirty data and invalidate
    void xthal_icache_all_unlock(void);
    void xthal_dcache_all_unlock(void);
    void xthal_L2_all_unlock(void);
 int32_t xthal_set_cache_prefetch(uint64_t mode);
 int32_t xthal_get_cache_prefetch(void);

Cache Region Control Functions
区域控制操作应用于内存中任意大小的连续字节序列。

   void xthal_icache_region_invalidate(void *addr, uint32_t size);
   void xthal_dcache_region_invalidate(void *addr, uint32_t size);
   void xthal_dcache_region_writeback(void *addr, uint32_t size);
   void xthal_dcache_region_writeback_inv(void *addr, uint32_t size);
   void xthal_icache_hugerange_invalidate(void *addr, uint32_t size);
   void xthal_dcache_hugerange_invalidate(void *addr, uint32_t size);
   void xthal_dcache_hugerange_writeback(void *addr, uint32_t size);
   void xthal_dcache_hugerange_writeback_inv(void *addr, uint32_t size);
   void xthal_dcache_L1_region_invalidate(void *addr, uint32_t size);
   void xthal_dcache_L1_region_writeback(void *addr, uint32_t size);
   void xthal_dcache_L1_region_writeback_inv(void *addr, uint32_t size);
   void xthal_icache_region_lock(void *addr, uint32_t size);
   void xthal_icache_region_unlock(void *addr, uint32_t size);
   void xthal_icache_hugerange_unlock(void *addr, uint32_t size);
   void xthal_dcache_region_lock(void *addr, uint32_t size);
   void xthal_dcache_region_unlock(void *addr, uint32_t size);
   void xthal_dcache_hugerange_unlock(void *addr, uint32_t size);
   void xthal_L2_region_lock(void *addr, uint32_t size);
   void xthal_L2_region_unlock(void *addr, uint32_t size);
int32_t xthal_set_region_attribute( void *vaddr, uint32_t size, uint32_t cattr, uint32_t flags );

Cache Block Control Functions (Block Prefetch)
缓存块控制操作类似于区域控制操作，因为它们适用于内存中可变大小的连续字节序列。但是，它们是使用块预取选项或缓存管理引擎选项提供的缓存块指令来实现的。

void xthal_dcache_block_invalidate(void *addr, uint32_t size);
void xthal_dcache_block_invalidate_max(void *addr, uint32_t size, uint32_t constmax);
void xthal_dcache_block_writeback(void *addr, uint32_t size);
void xthal_dcache_block_writeback_max(void *addr, uint32_t size, uint32_t constmax);
void xthal_dcache_block_writeback_inv(void *addr, uint32_t size);
void xthal_dcache_block_writeback_inv_max(void *addr, uint32_t size, uint32_t constmax);
void xthal_dcache_block_prefetch_for_read(void *addr, uint32_t size);
void xthal_dcache_block_prefetch_for_read_grp(void *addr, uint32_t size);
void xthal_dcache_block_prefetch_for_write(void *addr, uint32_t size);
void xthal_dcache_block_prefetch_for_write_grp(void *addr, uint32_t size);
void xthal_dcache_block_prefetch_read_write(void *addr, uint32_t size);
void xthal_dcache_block_prefetch_read_write_grp(void *addr, uint32_t size);
void xthal_dcache_block_prefetch_modify(void *addr, uint32_t size);
void xthal_dcache_block_prefetch_modify_grp(void *addr, uint32_t size);
void xthal_dcache_block_required_wait();
void xthal_dcache_block_wait();
void xthal_dcache_block_abort();
void xthal_dcache_block_end();
void xthal_dcache_block_newgrp();

Asynchronous Cache Operations
提供异步接口，支持缓存预取和降级操作。该接口仅在配置了二级缓存时有用。一次只允许一个异步操作，并且接口中的函数不可重入。因此，异步接口一次只能在一个线程中使用，并且不能在中断处理程序中使用，除非异步操作的所有用户禁用适用的中断。

   void xthal_async_L2_prefetch(void* addr, uint32_t size)
int32_t xthal_async_L2_region_lock(void* addr, uint32_t size)
    int xthal_async_L2_region_unlock(void* addr, uint32_t size)
int32_t xthal_async_L2_region_unlock(void)
   void xthal_async_L2_wait(void)
   void xthal_async_L2_prefetch_end(void)
int32_t xthal_async_dcache_region_writeback(void* addr, uint32_t size)
int32_t xthal_async_dcache_region_writeback_inv(void* addr, uint32_t size)
int32_t xthal_async_dcache_region_invalidate(void* addr, uint32_t size)
int32_t xthal_async_dcache_all_writeback_inv(void)
int32_t xthal_async_dcache_all_writeback(void)
int32_t xthal_async_dcache_all_invalidate(void)
   void xthal_async_dcache_wait(void)
int32_t xthal_async_dcache_busy(void)
   void xthal_async_dcache_abort(void)

Cache Line Control Functions and C macro
最后，还有在单个缓存线上操作的缓存控制函数。这些函数中的每一个都有一个地址参数addr，它标识一条缓存线。在addr未对齐的情况下，缓存行是包含addr指向的字节的行(即，地址隐式四舍五入)。

void xthal_icache_line_invalidate(void *addr);
void xthal_dcache_L1_line_invalidate(void *addr);
void xthal_dcache_L1_line_writeback(void *addr);
void xthal_dcache_L1_line_writeback_inv(void *addr);
void xthal_dcache_line_invalidate(void *addr);
void xthal_dcache_line_writeback(const void *addr);
void xthal_dcache_line_writeback_inv(const void *addr);
void xthal_icache_line_lock(void *addr);
void xthal_icache_line_unlock(void *addr);
void xthal_dcache_line_lock(void *addr);
void xthal_dcache_line_unlock(void *addr);
void xthal_L2_line_lock(void *addr);
void xthal_L2_line_unlock(void* addr);
void xthal_dcache_line_prefetch_for_write(void *addr);
void xthal_dcache_line_prefetch_for_read(void *addr);