module Key0_module ( clk, RSTn, Key_In, Key_Out ); input clk, RSTn; // "clk" is the clock input Key_In; // "Key_In" is the glitched, asynchronous, active low push-button signal output Key_Out; // 1 while the push-button is active (down) /***********************************************************/ // First use two flipflops to synchronize the Key signal the "clk" clock domain reg Key_sync_0; always @(posedge clk) Key_sync_0 <= ~Key; // invert Key_In to make Key_sync_0 active high reg Key_sync_1; always @(posedge clk) Key_sync_1 <= Key_sync_0; // Next declare a 16-bits counter reg [15:0] Key_cnt; // When the push-button is pushed or released, we increment the counter // The counter has to be maxed out before we decide that the push-button state has changed reg Key_Out; // state of the push-button (0 when up, 1 when down) wire Key_idle = (Key_Out==Key_sync_1); wire Key_cnt_max = &Key_cnt; // true when all bits of Key_cnt are 1's always @(posedge clk or negedge RSTn) if(!RSTn) Key_cnt <= 16'd0; else if(Key_idle) Key_cnt <=16'd0; // nothing's going on else begin Key_cnt <= Key_cnt + 1; // something's going on, increment the counter if(Key_cnt_max) Key_Out <= ~Key_Out; // if the counter is maxed out, Key_Out changed! end endmodule module top_module ( clk, RSTn, Data_out ); input clk, RSTn; output [1:0] Data_out; /**********************/ wire Key0_Out; Key0_moudle U1 ( .clk(clk), .RSTn(RSTn), .Key_Out(Key0_Out) ); /**********************/ wire Key1_Out; Key1_moudle U2 ( .clk(clk), .RSTn(RSTn), .Key_Out(Key1_Out) ); /**********************/ assign Data_out={Key1_Out,Key0_Out}; /**********************/ endmodule