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Verilog HDL
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xmjulytiger
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例化的方法实现多路开关量输入
module Key0_module( clk, RSTn, Key_In, Key_Out);input clk, RSTn; // "clk" is the clockinput Key_In; // "Key_In" is the glitched, asynchronous, active low push-button signaloutput Key_Ou原创 2011-06-28 08:04:00 · 454 阅读 · 0 评论 -
例化的方法实现多路编码器输入
module Decoder0( clk, RSTn, quadA, quadB, count);input clk, RSTn, quadA, quadB;output [7:0] count;reg [2:0] quadA_delayed, quadB_delayed;always @(posedge clk) quadA_delayed <= {quadA_del原创 2011-06-28 14:18:00 · 445 阅读 · 0 评论 -
6.27_5路正交脉冲量与24路开关量输入(脉冲量4倍频,开关量消抖,时钟同步)
/********************************************************************************************************** Five channels Decodre_Input which is being coded & tested by tiger**********************原创 2011-06-27 15:09:00 · 479 阅读 · 0 评论 -
Altera公司的PWM Verilog HDL源码(转帖自: http://www.61eda.com/Services/peixun/Altera/201103/2475.html)
顶层文件:/***************************************************************************//* File: pwm_avalon_interface.v *//* Description: Top level module. I转载 2011-06-29 21:57:00 · 2756 阅读 · 0 评论 -
sampling_moudle‘s V files(with 24 Keys, 5 Decoders)
module Decoder0( clk, RSTn, quadA, quadB, count);/************************************************************************************************/input clk, RSTn, quadA, quadB;output [15:0] c原创 2011-07-03 10:01:53 · 362 阅读 · 0 评论