vhdl_四位全加器设计方法(quartusll软件操作)

//元件例化法实现四位全加器

LIBRARY ieee;
USE IEEE.std_logic_1164.ALL;

ENTITY adder_xuchaoxin IS
    PORT (
        Ci : IN STD_LOGIC;
        a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        f : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        Co : OUT STD_LOGIC
    );
END adder_xuchaoxin;

ARCHITECTURE test OF adder_xuchaoxin IS
    SIGNAL c : STD_LOGIC_VECTOR(0 TO 4);
    
    COMPONENT adder_1bit_xuchaoxin --decalariton component
        -- PORT (--parameter
        --     Cin, x, y : IN STD_LOGIC;
        --     sum, Cout : OUT STD_LOGIC
        -- );--由于和该元件所对应的实体中的名字不一致,报错
        PORT (
            a, b, ci : IN STD_LOGIC;
            f, co : OUT STD_LOGIC);--注意这里的端口名要和该元件所对应的实体中的名字一致.
    END COMPONENT;
BEGIN
    c(0) <= Ci;
    U1 : adder_1bit_xuchaoxin PORT MAP(c(0), a(0), b(0), f(0), c(1));--map()~function();args come from the main entity adder_xuchaoxin
    U2 : adder_1bit_xuchaoxin PORT MAP(c(1), a(1), b(1), f(1), c(2));
    U3 : adder_1bit_xuchaoxin PORT MAP(c(2), a(1), b(1), f(2), c(3));
    U4 : adder_1bit_xuchaoxin PORT MAP(c(3), a(3), b(3), f(3), c(4));
    co <= c(4);
END test;

//元件例化法(需要一位全加器)

LIBRARY ieee;
USE IEEE.std_logic_1164.ALL;
ENTITY adder_1bit_xuchaoxin IS
    PORT (
        a, b, ci : IN STD_LOGIC;
        f, co : OUT STD_LOGIC);
END adder_1bit_xuchaoxin;

ARCHITECTURE testAdder OF adder_1bit_xuchaoxin IS
BEGIN
    f <= a XOR b XOR ci;
    co <= (a AND b) OR( a AND ci) OR( b AND ci);
    --use the logical operator.
END testAdder;

两个文件放在同一个Project下,可以通过如下方法添加到视图中:

检验当前的vhdl代码描述的电路是否符合预期(当然前提是你的代码通过编译了)
那么可以通过tools->Netlist_Viewers->RTL Viewer生产的电路示意图来对比一下: