cpacr_el1等特殊寄存器

CPACR_EL1, Architectural Feature Access Control Register
The CPACR_EL1 characteristics are:

Purpose

Controls access to trace, SVE, and Advanced SIMD and floating-point functionality.

浮点使能 需要操作该寄存器

FPEN

 bits [21:20]
Traps EL0 and EL1 accesses to the SIMD and floating-point registers to EL1, from both Execution  states.
00 -- Causes any instructions in EL0 or EL1 that use the registers associated with floating-point and Advanced SIMD execution to be trapped.
01 -- Causes any instructions in EL0 that use the registers associated with floating-point and Advanced SIMD execution to be trapped, but does not cause any instruction in EL1 to be trapped.
10-- Causes any instructions in EL0 or EL1 that use the registers associated with floating-point and Advanced SIMD execution to be trapped.

11 ---Does not cause any instruction to be trapped

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DBGPRCR_EL1,

Debug Power Control Register

Controls behavior of the PE on powerdown request.主要控制仿真器的调试发出powerdown请求，调试bare代码可以关注

CORENPDRQ, bit [0]
Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are:

0 On a powerdown request, the system powers down the Core power domain.

1 On a powerdown request, the system emulates powerdown of the Core power domain.

In this emulation mode the Core power domain is not actually powered down.
Writes to this bit are permitted regardless of the state of the IMPLEMENTATION DEFINED authentication interface. This means that a debugger can request Core no powerdown regardless of whether invasive debug is permitted

无论实现定义的身份验证接口处于什么状态，写入此位都是允许的。这意味着调试器可以请求Core no power down，而不管是否允许进行侵入式调试

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FAR_EL1 段错误的时候，会使用,data abort也会使用此寄存器
The FAR_EL1 characteristics are: 对应指令和数据abort的错误地址 或者 非对齐的pc地址
Purpose ---Holds the faulting Virtual Address for all synchronous instruction or data aborts, or exceptions from a misaligned PC or a Watchpoint debug event, taken to EL1
 

Bits [63:0]
Faulting Virtual Address for synchronous exceptions taken to EL1. Exceptions that set the
FAR_EL1 are instruction aborts (EC 0x20 or 0x21), data aborts (EC 0x24 or 0x25), a misaligned PC
exception (EC 0x22), or a Watchpoint exception (EC 0x34 or 0x35). ESR_EL1.EC holds the EC value
for the exception.
For a synchronous external abort other than a synchronous external abort on a translation table walk,
this field is valid only if ESR_EL1.FnV is 0, and the FAR_EL1 is UNKNOWN if ESR_EL1.FnV is 1.