• LIBRARY IEEE;
• USE ieee.std_logic_1164.ALL;
• USE ieee.std_logic_unsigned.ALL;
• ENTITY test34 IS
• PORT(clk,oe: IN std_logic;
• d: IN std_logic_VECTOR(7 DOWNTO 0);
• q: OUT std_logic_VECTOR(7 DOWNTO 0));
• END test34;
• ARCHITECTURE one OF test34 IS
• SIGNAL q_temp : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
• BEGIN
• PROCESS(clk,oe)
• BEGIN
• if oe='0' then
• if clk'event and clk='1' then q_temp<=d;
• end if;
• else q_temp<="ZZZZZZZZ";
• end if;
• END PROCESS;
• q<=q_temp;
• END ARCHITECTURE one ;