【VHDL】带使能端的同步复位的8位寄存器设计
程序:
library ieee;
use ieee.std_logic_1164.all;
entity reg8 is
port(clk,OE,RES:in std_logic;
A:in std_logic_vector(7 downto 0);
Q:out std_logic_vector
【VHDL】带使能端的同步复位的8位寄存器设计
程序:
library ieee;
use ieee.std_logic_1164.all;
entity reg8 is
port(clk,OE,RES:in std_logic;
A:in std_logic_vector(7 downto 0);
Q:out std_logic_vector