一、前言
计划使用VIVADO 2021.1中的video timing controller和AXI4-stream to video out IP核生成视频协议数据。
二、问题描述
调试过程中,出现LOCK信号无法锁定的问题,分析问题有以下两点:
- 需要保证video timing controller输出的时序与AXI stream的时序基本一致,主要是视频图像尺寸,比如图像大小为1024*600。
- 需要在AXI总线的ready信号有效时,让valid信号有效。以此保证AXI4-stream to video out IP核的underflow信号不拉高。
三、实现方案
各引脚的连接方式如RTL图。
四、IP核设置
video timing controller设置如下
AXI4-stream to video out IP设置如下
五、AXIS数据生成
module csi_to_axis(
input zu4cg_csi_pclk,
//AXIS 接口,输出到video out IP核
output reg [23 : 0] m_axis_video_tdata =0,
output wire m_axis_video_tvalid,
input wire m_axis_video_tready,
output wire m_axis_video_tuser,
output wire m_axis_video_tlast,
output wire m_axis_video_clk
);
localparam X_NUM = 11'd1024;//屏幕X方向像素点数
localparam Y_NUM = 10'd600;//屏幕Y方向像素点数
reg [11:0] pixel_cnt =0;
reg [11:0] line_cnt=0;
assign m_axis_video_clk = zu4cg_csi_pclk;
assign m_axis_video_tvalid = 1'b1;
always@(posedge zu4cg_csi_pclk)
begin
if(m_axis_video_tvalid & m_axis_video_tready)
m_axis_video_tdata <= m_axis_video_tdata + 1;
end
always@(posedge zu4cg_csi_pclk)
begin
if(m_axis_video_tvalid & m_axis_video_tready)begin
if(pixel_cnt < X_NUM-1)
pixel_cnt <= pixel_cnt +1;
else
pixel_cnt <= 'b0;
end
end
always@(posedge zu4cg_csi_pclk)
begin
if(m_axis_video_tvalid & m_axis_video_tready)begin
if(pixel_cnt == X_NUM-1)begin
if(line_cnt <Y_NUM -1)
line_cnt <= line_cnt + 1;
else
line_cnt <= 0;
end
end
end
assign m_axis_video_tuser = (line_cnt == 'b0 && pixel_cnt == 'b0
&&m_axis_video_tvalid && m_axis_video_tready)
?1'b1 :1'b0;
assign m_axis_video_tlast= (pixel_cnt == X_NUM-1)
?1'b1 :1'b0;
endmodule
六、仿真结果
仿真结果显示,LOCK信号正常锁定,AXI4-stream to video out输出正常。
完整工程下载链接:videotimingcontroller和AXI4-streamtovideooutIP核生成视频协议数据-嵌入式文档类资源-CSDN下载