module LED_TEST
(
input clk,
input rst,
output led
);
wire clk_50m;
wire clk_100m;
PLL PLL_inst (
.inclk0 ( clk ),
.c0 ( clk_50m ),
.c1 ( clk_100m )
);
CPU u0 (
.clk_clk (clk_50m), // clk.clk
.reset_reset_n (rst), // reset.reset_n
.led_conduit_end_led_export (led) // led_conduit_end.led_export
);
endmodule
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