PCIe4.0的Add-in-Card(AIC)金手指layout建议

116 篇文章 232 订阅

1.金手指下方的挖空和平面

对于支持16.0 GT/s的AIC,在金手指下方15mil以内,严禁有任何GND平面或电源平面,此区域的任何导体都会增加相对于高速信号线的电容,并且降低插损和增加回损。

内层的平面可以从板内向金手指方向延伸2mm,但需要注意GND平面距离金手指表面一定要大于15mil。

 

2.金手指长度

金手指长度为3.91mm(154.0 mil),整个金手指长度包含倒角区域为5.6mm。这种情况下,在金手指区域和倒角区域之间有0.39mm的空间,和Gen 1的4.3mm相比,金手指长度有所减少。在超出金手指下端0.13mm的区域中允许有少量的残留表面金属。任何活跃的PRSNT1#或PRSNT2# pin长度应该在3.2mm,无功能PRSNT2#金手指长度可以是3.2mm,也可以是3.91mm。

 3. AIC相邻的金手指地孔

AIC金手指的地孔必须分布在金手指相邻pin的正中间,这样可以减小信号出线的干扰。金手指上边缘到GND过孔的下边缘不能超过15mil。GND过孔和GND pin相连接的走线宽度必须大于等于过孔pad的直径,这样做是为了最小化接地电感。金手指的正反面GND pin可以共用GND过孔。

 4.合并金手指GND过孔

很多金手指GND pin相邻在一起,这种情况下,将和GND pin相连的GND过孔接在一起可以增加接地共振(ground resonance)。GND孔同样也可以两面共用。

 

  • 6
    点赞
  • 21
    收藏
    觉得还不错? 一键收藏
  • 打赏
    打赏
  • 1
    评论
Traditional multi-drop, parallel bus technology is approaching its practical performance limits. It is clear that balancing system performance requires I/O bandwidth to scale with processing and application demands. There is an industry mandate to re-engineer I/O connectivity within cost constraints. PCI Express comprehends the many I/O requirements presented across the spectrum of computing and communications platforms, and rolls them into a common scalable and extensible I/O industry specification. Alongside these increasing performance demands, the enterprise server and communications markets have the need for improved reliability, security, and quality of service guarantees. This specification will therefore be applicable to multiple market segments. Technology advances in high-speed, point-to-point interconnects enable us to break away from the bandwidth limitations of multi-drop, parallel buses. The PCI Express basic physical layer consists of a differential transmit pair and a differential receive pair. Dual simplex data on these point-to-point connections is self-clocked and its bandwidth increases linearly with interconnect width and frequency. PCI Express takes an additional step of including a message space within its bus protocol that is used to implement legacy “side- band” signals. This further reduction of signal pins produces a very low pin count connection for components and adapters. The PCI Express Transaction, Data Link, and Physical Layers are optimized for chip-to-chip and board-to-board interconnect applications. An inherent limitation of today’s PCI-based platforms is the lack of support for isochronous data delivery, an attribute that is especially important to streaming media applications. To enable these emerging applications, PCI Express adds a virtual channel mechanism. In addition to use for support of isochronous traffic, the virtual channel mechanism provides an infrastructure for future extensions in supporting new applications. By adhering to the PCI Software Model, today’s applications are easily migrated even as emerging applications are enabled.

“相关推荐”对你有帮助么?

  • 非常没帮助
  • 没帮助
  • 一般
  • 有帮助
  • 非常有帮助
提交
评论 1
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包

打赏作者

小孟boy

你的鼓励将是我创作的最大动力

¥1 ¥2 ¥4 ¥6 ¥10 ¥20
扫码支付:¥1
获取中
扫码支付

您的余额不足,请更换扫码支付或充值

打赏作者

实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值