IC菜菜子-CSDN博客

原创 1~8分频

module divider(input clk,input rst_n,input [2:0] divider_num, //0~7分别对应1~8分频 num[0]=0对应奇数分频output out_clk);reg [2:0] cnt1;reg clk_even;//偶数分频always @(posedge clk or negedge rst_n)beginif(!rst_n||!divider_num[0]) cnt1<=3'd0;else if(cnt1&l.

2021-09-05 12:41:40 154

原创计算n=log2(N)

module calc(input [159:0] N, //N=2^n;output [7:0] n);integer i;reg[7:0] cnt;reg [159:0] N_r;always @(*)beginN_r=N;cnt=8'd0;for(i=0;i<159;i=i+1)begin if(N_r[0]==0)begin N_r=N_r>>1; cnt=cnt+1; endendendassign n=cnt;endmodule.

2021-09-04 11:19:25 1251

原创 round-robin master

module arbiter(input clk,input rst_n,input [2:0] req, //req[0]:A,req[1]:B,req[2]:C;output reg[1:0] grant_out //2'b00 A获得总线，2'b01 B获得总线，2’10C获得);always @(posedge clk or negedge rst_n)begin if(!rst_n)begin grant_out <= 2'b11; //空闲 end else .

2021-09-04 11:17:51 110

原创乒乓buffer

module pingpong(clk,rst_n,data_in,data_out);input clk,rst_n;input [7:0] data_in;output reg [7:0] data_out;reg [7:0] buffer1;reg [7:0] buffer2;reg state; //0:写1读2,1：写二读1reg flag; //0:写1读2，1：写2读1always @(posedge clk or negedge rst_.

2021-09-04 11:15:25 296

原创握手协议实现

tx端：module woshou_tx(input rst_n,input t_clk,input ack,output [7:0] dout,output reg req);reg ack_reg1,ack_reg2;reg [7:0] data_buf;reg [7:0] TR_MEM_Addr;reg [7:0] TR_MEM [255:0];reg [2:0] cstate,nstate;parameter TR_IDLE=3'b000,SND_DATA_REQ=

2021-09-04 11:13:35 143

原创成绩统计排序

# -*- coding: utf-8 -*-"""Spyder EditorThis is a temporary script file."""def quick_sort(lists,i,j): if i >= j: return list pivot = lists[i] low = i high = j while i < j: while i < j and lists[j] >= .

2021-09-03 20:17:27 140

原创异步FIFO（寄存器存储）

module async_fifo( rst_n, fifo_wr_clk, fifo_wr_en, fifo_full, fifo_wr_data, fifo_rd_clk, fifo_rd_en, fifo_rd_data, fifo_empty); input rst_n; input fifo_wr_en; input fifo_rd_en; input fifo_rd_clk; input fifo_wr_clk; input [7:0] fifo_wr_.

2021-09-03 20:15:26 661

原创异步FIFO（RAM存储）

module async_fifo(rst_n,fifo_wr_clk,fifo_wr_en,r_fifo_full,fifo_wr_data,fifo_rd_clk,fifo_rd_en,fifo_rd_data,r_fifo_empty);input rst_n;input fifo_wr_en;input fifo_rd_en;input fifo_rd_clk;input fifo_wr_clk;input [7:0] fifo_...

2021-09-03 20:11:35 340

原创统计次大值出现次数

一个模块，input有clk，rstn，10bit随机数，output为曾经出现过的次大值以及次大值出现的次数。module comp_secmax(input clk,input rstn,input [9:0]data,output reg [9:0] sec_max,output reg [9:0] cnt_sec_max);reg [9:0] data_in;reg [9:0] max;reg [9:0] cnt_max;always @(posedge clk or n

2021-07-13 20:42:47 389

原创 HDLbits Edgecapture

module top_module ( input clk, input reset, input [31:0] in, output [31:0] out); reg [31:0] in_dly; always @(posedge clk)begin in_dly<=in; if(reset) out<= 32'd0; else if(~in&in_dly) .

2021-06-10 11:25:34 231 1

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