乒乓buffer

module pingpong(

clk,
rst_n,
data_in,
data_out

);

input clk,rst_n;
input [7:0] data_in;
output reg [7:0] data_out;

reg [7:0] buffer1;
reg [7:0] buffer2;
reg state;        //0:写1读2,1：写二读1
reg flag;  //0:写1读2，1：写2读1

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		state<=1'b0;
	end
	else
		state<=!state;
end

always @(*)begin
	case(state)
	1'b0:begin
		flag<=1'b0;
	end
	1'b1:begin
		flag<=1'b1;
	end
	default:
		flag<=1'b0;
	endcase
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		buffer1<=8'd0;
		buffer2<=8'd0;
	end
	else if(!flag) begin
		buffer1<=data_in;
		data_out<=buffer2;
	end
	else begin
		buffer2<=data_in;
		data_out<=buffer1;
	end	
end

endmodule