round-robin master

module arbiter(
input clk,
input rst_n,
input [2:0] req,  //req[0]:A,req[1]:B,req[2]:C;
output reg[1:0] grant_out //2'b00 A获得总线，2'b01 B获得总线，2’10C获得
);

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		grant_out <= 2'b11;  //空闲
	end
	else begin
		case(grant_out)
			2'b00:
				case(req)
					3'b000:grant_out<=2'b00;  //无请求,总线保持
					3'b001:grant_out<=2'b00;
					3'b010:grant_out<=2'b01;
					3'b011:grant_out<=2'b01;
					3'b100:grant_out<=2'b10;
					3'b101:grant_out<=2'b10;
					3'b110:grant_out<=2'b01;
					3'b111:grant_out<=2'b01;
				endcase
			2'b01:
				case(req)
					3'b000:grant_out<=2'b01;  //无请求,总线保持
					3'b001:grant_out<=2'b00;
					3'b010:grant_out<=2'b01;
					3'b011:grant_out<=2'b00;
					3'b100:grant_out<=2'b10;
					3'b101:grant_out<=2'b10;
					3'b110:grant_out<=2'b10;
					3'b111:grant_out<=2'b10;
				endcase
			2'b10:
				case(req)
					3'b000:grant_out<=2'b10;  //无请求,总线保持
					3'b001:grant_out<=2'b00;
					3'b010:grant_out<=2'b01;
					3'b011:grant_out<=2'b00;
					3'b100:grant_out<=2'b10;
					3'b101:grant_out<=2'b00;
					3'b110:grant_out<=2'b01;
					3'b111:grant_out<=2'b00;
				endcase
		default:grant_out<=2'b00;
		endcase	
	end
end

endmodule