fpga verilog 流水灯

verilog 流水灯试验
原理图

ledloop.v

module ledloop(
  input wire clk,
  output wire[3:0] LED 
);
localparam OSC = 32'd50_000_000;

  reg[31:0] cnt = 32'h00000000;
  reg[31:0] scnt = 32'h00000000;

  always @(posedge clk)
    if (cnt == OSC) begin
      cnt <= 32'h000000000;
      scnt <= scnt+1;
    end else
    	cnt <= cnt + 1;
    	
  assign LED = 4'b0001 << scnt[1:0];
                                                                                                                             
  endmodule

约束
ledloop.sdc

create_clock -name clk -period "50MHz" [get_ports clk]
set_false_path -from * -to [get_ports LED[0]]
set_false_path -from * -to [get_ports LED[1]]
set_false_path -from * -to [get_ports LED[2]]
set_false_path -from * -to [get_ports LED[3]]

50M晶振，1秒移一位。

资源占用

rtl