【FPGA】verilog流水灯实验

用三个拨码开关去控制7个LED灯，具体要求：
拨下000七个灯全灭；
拨下001只亮第一个灯，按1s的频率闪烁；
拨下010前两个灯以1s的频率依次闪烁，即LED0亮1s，切换到LED1亮1s，然后切换到LED0亮1s。
…
拨下111七个灯以1s的频率依次闪烁，即LED0亮1s，切换到LED1亮1s，切换到LED2亮1s……切换LED6亮1s，切换到LED0亮1s。

实现代码：

module LED_run #(
//    parameter [26:0] change_time = 27'h5f5_e0ff
	parameter [26:0] change_time = 27'h5
)
(
	input clk_p,
	input clk_n,
	input reset,
	input [2:0] switch,
	output [6:0] LED
);

//使用了差分时钟
    IBUFDS #(
      .DIFF_TERM("FALSE"),       // Differential Termination
      .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" 
      .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
   ) 
    IBUFDS_inst (
      .O(clk),  // Buffer output
      .I(clk_p),  // Diff_p buffer input (connect directly to top-level port)
      .IB(clk_n) // Diff_n buffer input (connect directly to top-level port)
   ); 
	
	reg [26:0] timer;
	reg [6:0] LED_tmp;
	reg [2:0] switch_reg;
	
	always @(posedge clk or negedge reset) begin
		if(!reset)
			timer <= 27'h0;
		else if(timer == change_time | switch != switch_reg)
			timer <= 27'h0;
		else
			timer <= timer + 1;
	end
	
	always @(posedge clk or negedge reset) begin
		if (!reset)
			LED_tmp <= 7'h00;
		else if(switch != switch_reg) begin
		  LED_tmp <= ((switch == 3'b000)? 7'h00:7'h01);
		end
		else if(timer == change_time) begin
			case(switch)
				3'b000:		LED_tmp <= LED_tmp;
				3'b001:		LED_tmp <= {LED_tmp[6:5], ~LED_tmp[0]};
				3'b010:		LED_tmp <= {LED_tmp[6:2], LED_tmp[0], LED_tmp[1]};
				3'b011:		LED_tmp <= {LED_tmp[6:3], LED_tmp[1:0], LED_tmp[2]};
				3'b100:		LED_tmp <= {LED_tmp[6:4], LED_tmp[2:0], LED_tmp[3]};
				3'b101:		LED_tmp <= {LED_tmp[6:5], LED_tmp[3:0], LED_tmp[4]};
				3'b110:		LED_tmp <= {LED_tmp[6], LED_tmp[4:0], LED_tmp[5]};
				3'b111:		LED_tmp <= {LED_tmp[5:0], LED_tmp[6]};
				default:    LED_tmp <= 7'h00;
			endcase
		end
    end
	
	always @(posedge clk or negedge reset) begin
        if(!reset)
            switch_reg <= 3'b000;
        else
            switch_reg <= switch;
	end
	
	assign LED = LED_tmp;

endmodule

测试代码：

`timescale 1ns/1ps

`define clk_period 10

module LED_tb;

	reg Clk_p;
	reg Clk_n;
	reg rst_tb;
	reg [2:0] switch_tb;
	wire	[6:0] LED_tb;
//	reg [26:0] sec = 27'h5f5_e0ff;
    reg [26:0] sec = 27'h5;
	
	LED_run LED_run1(
		.clk_p(Clk_p),
		.clk_n(Clk_n),
		.rst_n(rst_tb),
		.switch(switch_tb),
		.LED(LED_tb)
	);
	
	initial begin
		Clk_p = 0;
		Clk_n = 1;
		rst_tb = 1'b0;
		switch_tb = 3'b000;
		#50;
		rst_tb = 1'b1;
		#50;
		switch_tb = 3'b000;
		#(sec * 10);
		switch_tb = 3'b001;
		#(sec * 25);
		switch_tb = 3'b010;
		#(sec * 25);
		switch_tb = 3'b011;
		#(sec * 45);
		switch_tb = 3'b100;
		#(sec * 65);
		switch_tb = 3'b101;
		#(sec * 85);
		switch_tb = 3'b110;
		#(sec * 105);
		switch_tb = 3'b111;
		#(sec * 125);
		switch_tb = 3'b000;
		#(sec * 145);
		$stop;
	end
	
	always #(`clk_period/2) Clk_p = ~Clk_p;
	always #(`clk_period/2) Clk_n = ~Clk_n;
endmodule

仿真波形：