75M的写操作配置

最新推荐文章于 2022-12-08 06:00:00 发布

zealane

最新推荐文章于 2022-12-08 06:00:00 发布

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下面是75M的写操作配置。
XintfRegs.XTIMING2.bit.XWRTRAIL = 1;    // 0 // 3 // 1
XintfRegs.XTIMING2.bit.XWRACTIVE = 0;   // 0 // 2 // 0
XintfRegs.XTIMING2.bit.XWRLEAD = 1;     // 1 // 2 // 1
目前2812单板按照这样的配置，电机仿真测试都比较稳定。
void InitXintf(void)
{
    // Example of chaning the timing of XINTF Zones.
    // Note acutal values should be based on the hardware
    // attached to the zone - timings presented here are
    // for example purposes.
    // All Zones:
    // Timing for all zones based on XTIMCLK = SYSCLKOUT
    XintfRegs.XINTCNF2.bit.XTIMCLK = 0; // XTIMCLK 0:= SYSCLKOUT 1:= 1/2 SYSCLKOUT
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;      // 0: enable CLKOUT      1: Disable CLKOUT
    XintfRegs.XINTCNF2.bit.CLKMODE = 0;      // XCLKOUT 0:= XTIMCLK    1:= 1/2 XTIMCLK
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    // Zone 0:
    // Change write access lead active trail timing
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Use timings based on SYSCLKOUT = XTIMCLK
    XintfRegs.XTIMING0.bit.USEREADY = 0;
    XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
    XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING0.bit.XWRLEAD = 2;
    XintfRegs.XTIMING0.bit.XRDTRAIL= 3;
    XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING0.bit.XRDLEAD = 2;
    // Do not double lead/active/trail for Zone 0
    XintfRegs.XTIMING0.bit.X2TIMING = 1;
    /*************************************************
         CPLD可靠读写的时序参数设置
         (CPLD时钟为100.00MHz)
     *************************************************/
#if 0
    XintfRegs.XTIMING1.bit.USEREADY = 0;
    XintfRegs.XTIMING1.bit.XWRTRAIL = 1;
    XintfRegs.XTIMING1.bit.XWRACTIVE = 1;
    XintfRegs.XTIMING1.bit.XWRLEAD = 2;
    XintfRegs.XTIMING1.bit.XRDTRAIL= 1;
    XintfRegs.XTIMING1.bit.XRDACTIVE = 2;
    XintfRegs.XTIMING1.bit.XRDLEAD = 2;
    // Do not double lead/active/trail for Zone 0
    XintfRegs.XTIMING1.bit.X2TIMING = 0;
#else
    XintfRegs.XTIMING1.bit.USEREADY = 0;
    XintfRegs.XTIMING1.bit.XWRTRAIL = 3;   // 3 // 3
    XintfRegs.XTIMING1.bit.XWRACTIVE = 3; // 2 // 3
    XintfRegs.XTIMING1.bit.XWRLEAD = 2;    // 1 // 2
    XintfRegs.XTIMING1.bit.XRDTRAIL= 3;    // 2 // 3
    XintfRegs.XTIMING1.bit.XRDACTIVE = 3; // 1 // 3
    XintfRegs.XTIMING1.bit.XRDLEAD = 2;    // 1 // 2
    // Do not double lead/active/trail for Zone 0
    XintfRegs.XTIMING1.bit.X2TIMING = 1;
#endif
    /*************************************************
         SRAM可靠读写的时序参数设置
     *************************************************/
    // Zone 2
    // Ignore XREADY for Zone 2 accesses
    // Change read access lead/active/trail timing
    XintfRegs.XTIMING2.bit.USEREADY = 0;
    XintfRegs.XTIMING2.bit.XSIZE    = 3;
    XintfRegs.XTIMING2.bit.XWRTRAIL = 1;    // 0 // 3 // 1
    XintfRegs.XTIMING2.bit.XWRACTIVE = 0;   // 0 // 2 // 0
    XintfRegs.XTIMING2.bit.XWRLEAD = 1;     // 1 // 2 // 1
    XintfRegs.XTIMING2.bit.XRDTRAIL= 2;     // 2 // 3 // 1
    XintfRegs.XTIMING2.bit.XRDACTIVE = 1;   // 1 // 2 // 0
    XintfRegs.XTIMING2.bit.XRDLEAD = 1;      // 1 // 2 // 1
    XintfRegs.XTIMING2.bit.X2TIMING = 0;
    // Zone 2 is slow, so add additional BCYC cycles when ever switching
    // from Zone 2 to another Zone. This will help avoid
    // bus contention.
    XintfRegs.XBANK.bit.BCYC = 2;
    XintfRegs.XBANK.bit.BANK = 2; // 2
}