http://www.openhw.org/module/forum/thread-644643-1-1.html
Place the Verilog constraint immediately before the module or instantiation .
Specify the Verilog constraint as follows:
(* KEEP = “{TRUE|FALSE |SOFT}” *)
假如我们要观察的一个信号cnt:reg [10:0] cnt;,那么就按照文档中的介绍,要保持此信号不被综合,则:
(* KEEP = “TRUE” *) reg [10:0] cnt ,或者 (* keep= “true” *) reg [10:0] cnt
这样就可以实现ChipScope的观察而不被优化掉了。类似的VHDL: