xilinx搭建axi转avalon通用寄存器读写模块

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已于 2025-01-06 14:22:27 修改

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文章标签： fpga开发

于 2024-12-11 14:40:38 首次发布

本文链接：https://blog.csdn.net/zhangkui469226425/article/details/144400615

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1，axi转avalon bridge配置
在这里插入图片描述
2，block design结构

3，reg_ctrl.v代码
注意M_AVALON_address要右移两位

module reg_ctrl (
    input           clk             ,
    input           rst             ,

    input       [7:0]   M_AVALON_address           ,
    input               M_AVALON_read              ,
    output reg  [31:0]  M_AVALON_readdata          ,
    input               M_AVALON_write             ,
    input       [31:0]  M_AVALON_writedata         ,

    //gpio
    input       [3:0]       pid_VER_SEL ,
    input       [7:0]       pid_IP_SW   ,
    output reg  [7:0]       pod_CAN_LED 
);

    wire  [7:0]     fpga_prj_ver_h;
    wire  [7:0]     fpga_prj_ver_m;
    wire  [7:0]     fpga_prj_ver_l;

    reg         M_AVALON_write_r        ;
    reg [7:0]   M_AVALON_address_r      ;
    reg [31:0]  M_AVALON_writedata_r    ;


    assign  fpga_prj_ver_h  = 8'd0;  
    assign  fpga_prj_ver_m  = 8'd0;           //版本号
    assign  fpga_prj_ver_l  = 8'd1;            //



/****************************************************************************************/
    always@(posedge clk) begin
        M_AVALON_write_r        <=  M_AVALON_write        ;
        M_AVALON_address_r      <=  M_AVALON_address      ;
        M_AVALON_writedata_r    <=  M_AVALON_writedata    ;
    end

    always @(posedge clk) begin
        if(rst) begin
            pod_CAN_LED <= 8'h00;
        end
        else if(M_AVALON_write_r) begin
            case({M_AVALON_address_r[7:0]})
            8'h03 : pod_CAN_LED		        <= M_AVALON_writedata_r[7:0]		;

            endcase
        end
    end

    always @(posedge clk)begin
        if(M_AVALON_read)begin
            case(M_AVALON_address[7:0])
            8'h00 : M_AVALON_readdata	<= {8'b0, fpga_prj_ver_h, fpga_prj_ver_m, fpga_prj_ver_l}		;
            8'h01 : M_AVALON_readdata	<= {28'b0, pid_VER_SEL}	;
            8'h02 : M_AVALON_readdata	<= {24'b0, pid_IP_SW  }	;
            8'h03 : M_AVALON_readdata	<= {24'b0, pod_CAN_LED}	;

            default: begin
                M_AVALON_readdata  <= 32'hzzzz			;
            end
		    endcase
        end
    end

/****************************************************************************************/

4，c代码

#define ReadFPGAReg(addr)		(*(volatile unsigned long *)(XPAR_M_AVALON_0_BASEADDR + ((addr) << 2)))
#define WriteFPGAReg(addr,data) (*(volatile unsigned long *)(XPAR_M_AVALON_0_BASEADDR + ((addr) << 2))) = data