Verilog设计“111”检测器与“01110”检测器并测试所有情况

Verilog实现“111”检测器与“01110”检测器的设计

使用Quartus+modelsim完成本次设计

1. "111"检测器

分析

分析题目，得到其有限状态机为下图：

代码实现

module detector111(
	input X,
	input rst,
	input clk,
	output OUT
);
	reg [1:0]state;
	reg [1:0]next_state;
	parameter S0=2'd0,S1=2'd1,S2=2'd2,S3=2'd3;
	
	assign OUT = (state==S3)?1:0;			//define OUT=1 when S3 state
	
	
	always @ (posedge clk or posedge rst) 
		if (rst)
			state  <=  S0;
		else
			state  <=  next_state;
	
	always@(*)
		case(state)
		S0:if(X) next_state <= S1;
			else 	next_state <= S0;
		S1:if(X)	next_state <= S2;
			else  next_state <= S0;
		S2:if(X)	next_state <= S3;
			else	next_state <= S0;
		S3:if(X) next_state <= S3;
			else  next_state <= S0;
		default: next_state <= S0;
		endcase

endmodule 

Testbench

`timescale 1 ns/ 1 ns
module detector111_vlg_tst();
reg X;
reg clk;
reg rst;                                            
wire OUT;
                      
detector111 i1 (
	.OUT(OUT),
	.X(X),
	.clk(clk),
	.rst(rst)
);
	always #10 clk = ~clk;
	initial                                                
		begin                                                  
			 rst = 1;
			 clk = 0;
			#10 rst = 0; 
			#20 X = 1;
			#20 X = 0;
			#20 X = 1;
			#20 X = 1;
			#20 X = 1;
			#20 X = 1;
			#20 X = 0;
			#20 X = 1;
			#20 X = 0;
			#20 X = 1;
			#20 X = 1;
			#20 X = 1;
			#20 X = 1;
			#20 $stop;
		end				
	initial $monitor($time,"X=%b,OUT=%b",X,OUT);
endmodule

结果

Modelsim结果如下图所示，分析可知实现了题目要求。

逻辑综合出来的电路如下图所示：即只有S3状态才会输出OUT=1。

其中的state的状态机如下图所示（RLT viewer中所示），可见其与分析中绘制的状态机一致。

---

2. "01110"检测器

分析

题目中关键点为一下几点：

• 检测01110，且他们不重叠。意思为要求检测到一个01110，然后从一个新的开始检测。
• 同时输入AB，那么考虑A和B哪个是01110的开始标志
• Z输出的是一个时钟周期宽度的高电平脉冲，所以要在always里进行赋值

根据题目绘制状态机如下图所示，其中S0表示01110中的0，以此类推，特别注意S1表示第一位是1即没有意义。其中输出为1即检测出01110的状态用红色标出

如果要测试所有情况，那么就是讲detector01110模块中的所有case模块都遍历到，及遍历以下所有情况，需要修改的只有testbench。而如果遍历所有情况，通过分析知道，每次AB的状态为2bit数，可以理解为4种前进的方向，然后一共5个状态，那么要遍历的次数为4^5=1024种情况，遍历即可。

			case(state)
			S0:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S011;
			endcase
			S01:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S0111;
			endcase		
			S011:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S1;
				4'b11:state<=S1;
			endcase			
			S0111:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S1;
			endcase
			S1:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S1;
			endcase	

代码实现

module detector01110(
	input clk,
	input clr,
	input A,
	input B,
	output reg Z	
);
	reg [3:0]state;
	parameter	S0 = 4'b0,
			  	S01 = 4'b01,
			  	S011 = 4'b011,
				S0111 = 4'b0111,
				S1 = 4'b10;//S1 is random because S01 has already existed
	always@(posedge clk or negedge clr)
	begin
	if(!clr) 
		begin 
		state <= S0;
		Z<=0;		
		end //for {A,B}=4'b00;
	else 
		begin
			Z = (state==S011&{A,B}==4'b10 | state==S0111&A==4'b0)?1:0;
			case(state)
			S0:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S011;
			endcase
			S01:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S0111;
			endcase		
			S011:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S1;
				4'b11:state<=S1;
			endcase			
			S0111:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S1;
			endcase
			S1:case({A,B})
				4'b00:state<=S0;
				4'b01:state<=S01;
				4'b10:state<=S0;
				4'b11:state<=S1;
			endcase		
		endcase		
		end	
	end
endmodule 

Testbench

`timescale 1 ns/ 1 ns
module detector01110_vlg_tst();
reg A;
reg B;
reg clk;
reg clr;
// wires                                               
wire Z;
                      
detector01110 ins1 (
// port map - connection between master ports and signals/registers   
	.A(A),
	.B(B),
	.Z(Z),
	.clk(clk),
	.clr(clr)
);
	always #10 clk = ~clk;
	
	integer i0;
	integer i1;
	integer i2;
	integer i3;
	integer i4;
	//5 layers circulation
    //4^5=1024
	initial                                                
		begin                                                  
			clr = 0;
			clk = 0;
			{A,B} = 4'b00;
			#15 clr = 1; 
			for(i0=0;i0<4;i0=i0+1)
			begin
				#20 {A,B} = i0;
				for(i1=0;i1<4;i1=i1+1)
				begin
					#20 {A,B} = i1;
					for(i2=0;i2<4;i2=i2+1)
					begin 
						#20 {A,B} = i2;
						for(i3=0;i3<4;i3=i3+1)
						begin
							#20 {A,B} = i3;
							for(i4=0;i4<4;i4=i4+1)
								#20 {A,B} = i4;
						end		
					end	
				end	
			end					
			#50 $stop;
		end			
		
	initial $monitor($time,"Z=%b",Z);
endmodule

结果

Modelsim仿真结果如下所示，经分析与预期一致

逻辑综合后的结果如下图所示：

state里的状态机如下图所示，符合预期：