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原创 SSN ( Streaming Scan Network ) 是什么？

大型片上系统(SoC)设计的复杂性不断增加，这对包括测试设计(DFT)在内的所有IC设计学科都提出了挑战。为了缓解这些挑战，层次DFT被用作一种分而治之的方法，其中所有DFT实现，包括模式生成和验证，都是在核心级别而不是芯片级别完成的。然而，层次DFT本身已经不够了。DFT工程师必须在测试实现工作和制造测试成本之间做出权衡。本文介绍了测试流扫描网络(SSN)的基本组成部分，SSN是一种封装测试交付技术，旨在解耦核心级和芯片级DFT需求。

原创 SRAM 测试总结

SoC随着工艺进步设计复杂度增加，embeded sram也越来越多。在40nm SoC产品Sram一般在20Mbits左右，当工艺发展到28nm时Sram就增加到100Mbits。如果考虑AI产品，Sram估计更多。如何更好的测试Sram就成为量产测试的重中之重。Sram的结构一个6T sram cell的经典结构如图所示：这些Sram cell集合成如下图的多个bank的memory block，每个bank有bank address使能；在一个bank内Row address选择

原创 CheckPins

Extracted Timing Model Contains Internal Pins With the Name of the Master ClockDescriptionQuestion:In an extracted timing model (ETM), there is an internal pin with the name of the master clock. What is the reason for it?Answer:In an extracted ti

原创 IC Open/Short/Leakage 测试

开短路测试(open_short_test)又叫continuity test 或contact test,它是一种非常快速发现芯片的各个引脚间的是否有短路，及在芯片封装时是否missing bond wires.通常都会被放测试程序的最前面.它还能发现测试时接触是否良好，探针卡或测试座是否有问题.开短路测试的测试原理比较简单，分open_short_to_VDD 测试和open_short_to_VSS测试.一般来说芯片的每个引角都有泄放或说保护电路,是两个首尾相接的二...

原创 Control Timings in VCS

VCS/VCSMX can disable module path delays as well as timing checks at various levels of granularity viz. on the entire design, on a specific module or on a specific timing arc in a specific instance. 1. Disabling delays and timing checks on the entire .

原创 How Do Wrapper Chains and Wrapper Cells Work in Detail?

DescriptionQuestion:I am using the core wrapper feature of the DFTMAX tool. The user guide describes wrapper chain behavior from a high level, but it does not show detailed wrapper chain timing diagrams or logic schematics. In detail, how do wrapper ch

原创 How do I make VCS ignore timing between synchronizer flops?

Question:How do I make VCS ignore SDF timing between synchronizer flip flops in my full timing gate simulation?Answer:VCS accepts configuration file that can enable/disable certain features and options.One of these features is the ability t

原创 How Are Clock Gating Checks Inferred?

I have many clock gating checks in my design. Some of my clock gating checks are complex, where the gating signal is launched by a different clock than the clock being gated. What are the rules for how the setup and hold clock gating checks are inferred?

原创 How Does Clock Reconvergence Pessimism Removal (CRPR) Handle Dynamically Switched Related Clocks?

I have a design in which a clock network switches between the original and divide-by-two version of a clock:Figure 1: Clock NetworkThe clock switching circuitry is designed so that I can switch between them "on the fly" during the low portion of.

原创 Why Is My CRPR Common Point Incorrect?

I have a design with a path similar to the following:Figure 1: Design PathAll buffers have min/max delays of 1ns/2ns, with the exception of U3 which has a slow delay of 1.9ns instead of 2ns (represented with a slightly smaller buffer symbol). When ..

原创 CMOS Basics & Process Overview

Why CMOS?Output of all CMOS cells will be very close to rail-rail (may not be in case of Pass Transistor) With constant input to any cell, power dissipation is only due to leakage currents. Power dissipation increase if activity factor is more (Short ci

原创 STA Part 2 by signoff-scribe

Ways to fix setup violations:Setup violation occurs because of high delay in the data path or due to negative skew.Below are the ways to fix setup violation:Gate sizing Buffering Cloning Logic restructuring Vt swapping SkewingGate Sizing:Thi

原创 Wire Modelling, Cross-talk & Double-switching

WireWire appears as a simple line in schematic diagrams, connecting two components. But they are equally important as transistors because they affect speed, power dissipation and reliability of the circuit.Wire ModelGenerally we think of wire to be i

原创 STA – Part1

What is STA ?Static timing analysis is one of the techniques used to verify the timing of a digital design. STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pi

原创 Clarification for SMS Wrapper synthesis and STA timing exceptions

1.This section contains theexplanation of the timing exceptions forsn6xx000vpnnsmwrp000sa18SMS Wrapper.Compared withSMS 5.x, where data exchange between fast and slow clock domains happens, in SMS 6x, due to the clock switching mechanism, communicati...

转载 Multi chip package多芯片封装技术对比

1. 传统多芯片模块封装技术Die 2 Die的通信是通过基板电路实现的，优点是可靠，缺点是集成的密度比较低。是一种非常原始的方式。例子：amd Naples 的四个Chiplet之间的通信也是使用这种方式。2. 使用硅中介层的封装技术 -2.5D封装Silicon Interposer起承上启下的作用缺点是：增加了厚度，增加了成本，所有Die出去的型号都要通过TSV技术过孔原本不必要，增加了成本。目前工业界大部分的单封装的处理器基本都是这种封装技术。例子：...

原创 DFT compiler

scanjtagbistip

原创 IEEE std 1149.1 JTAG bscan 原理

jtag

原创 ATPG 基础

scan 测试

原创 STA - PVT、RC、OCV

PVTPVT是工艺、电压和温度的缩写。为了让我们的芯片在所有可能的条件下工作，比如在锡亚琴冰川-40°C和撒哈拉沙漠60°C，我们模拟了IC在制造后可能面临的不同过程、电压和温度的条件。这些条件称为corner。这三个参数都影响到cell的延时。我们将详细地讨论每个参数及其对延迟的影响。Process:工艺变化是指晶体管在制造过程中属性的偏差。在裸片die制造过程中，die的中心和边界处的区域可能会有不同的工艺变化。这是因为将被制造的层不能在整...

原创 STA - clock gating timing check

原创 STA - 不同时钟域之间插入latch，fix hold违例

如图所示，数据由寄存器 F1 发出，寄存器 F3 捕获，完成CTS之后，由于clock skew原因，F1 到 F3 的hold，较难满足。在F1与F3之间插入一个latch，latch的时钟接start point时钟，即CLK1。latch为高电平透明，低电平锁存。则F1-F3的path分成两段。setup检查可以分两段检查，也可以是一段检查（latch作为组合逻辑看待）。hold检查只能分成两段检查。这样F1->L2的hold检查：在L2的close edge沿检查hold，因为是同

原创 STA - Exceptions：set_multicycle_path

1. launch clock and capture clock have the same clock frequencyPT工具默认检查行为：设置multicycle path，setup：3，hold：22. fast launch clockto slow capture clockPT工具默认检查行为：设置multicycle path，setup：3，hold：2，必须指定-start选项。3. slow launch clock to f...

原创 STA - Clock Groups：set_clock_groups

set_clock_groupsset_clock_groups 命令有三个选项：“-asynchronous”，“-logically_exclusive”，“-physically_exclusive”当 set_clock_groups 命令中多个 groups 被指定时，同一个时钟不能出现在不同的 group 中，但是可以存在于多次set_clock_groups 命令使用。例如 set_clock_groups -asynchronous -group {ClkA ClkB} -g..

原创 Physical implementation —— LEF and DEF

LEFLEF 是Library Exchange Format 的首字母缩写，是C 家物理库的描述格式。LEF 分为tech lef 跟cell lef 两种，不论是哪个阶段的工具要使用lef 都必须先读入tech lef 再读入cell lef, 因为cell lef 中要引用tech lef 中定义的信息。Tech lef 中定义了metal layer, via, design rule 等信息，请详细研读下面几张从油管上抠出来的图，图中较详细介绍了tech lef, cell lef 各包含