组合电路时序弧

Nonsequential Timing Arcs
在某些组合逻辑单元中，在数据引脚上指定建立和保持时间的时序约束，并使用非时钟引脚作为相关引脚。
它要求一个引脚的信号在同一单元范围状态的另一个引脚之前和之后的指定时间内保持稳定，以便该单元能够按预期的方式工作。
(1)non_seq_setup_rising
定义(使用NON_SEQ_SETUP_FALLING)用于在具有组合逻辑行为的点之间进行建立时间检查的时序弧。“_Rise”标识告诉“Design Compiler”工具，相关接点的上升边处于激活状态，以便进行建立检查。
(2)non_seq_setup_falling
Defines (with non_seq_setup_rising) the timing arcs used for setup checks between pins with nonsequential behavior. The related pin in a timing arc is used for the timing check. The _falling designation tells the Design Compiler tool that the falling edge of the related pin is active for the setup check.
(3) non_seq_hold_rising
Defines (with non_seq_hold_falling) the timing arcs used for hold checks between pins with nonsequential behavior. The related pin in a timing arc is used for the timing check. The _rising designation tells the Design Compiler tool that the rising edge of the related pin is active for the hold check.
(4) non_seq_hold_falling
Defines (with non_seq_hold_rising) the timing arcs used for hold checks between pins with nonsequential behavior. The related pin in a timing arc is used for the timing check. The _falling designation tells the Design Compiler tool that the falling edge of the related pin is active for the hold check.