单总线缓冲器代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sinnal_buffer IS
PORT(a: IN STD_LOGIC_VECTOR(0 TO 7);
enable_control:IN STD_LOGIC;
c:OUT STD_LOGIC_VECTOR(0 TO 7));
END ENTITY sinnal_buffer;
ARCHITECTURE archit_state OF sinnal_buffer IS 
BEGIN
PROCESS(a,enable_control)
BEGIN
IF enable_control='1'THEN
c<=a;
ELSE 
c<="ZZZZZZZZ";
END IF;
END PROCESS;
END ARCHITECTURE archit_state;