1、CC2420与处理器相连的引脚有:
RESETn:Asynchronous, active low digital reset
VREG_EN:Voltage regulator enable, active high, held at VREG_IN voltage level when active
SFD:SFD (Start of Frame Delimiter) / digital mux output
CCA:CCA (Clear Channel Assessment) / digital mux output
FIFOP:High when number of bytes in FIFO exceeds threshold / serial RF clock output in test mode
FIFO:High when data in FIFO / serial RF data input / output in test mode
CSn:SPI Chip select, active low
SCLK:SPI Clock input, up to 10 MHz
SI:SPI Slave Input. Sampled on the positive edge of SCLK
SO:SPI Slave Output. Updated on the negative edge of SCLK. Tristate when CSn high. Programmable internal pullup
2、Stargate2 中CC2420与PXA引脚定义:
#define SG2_GPIO34_SSPSCLK (34 | GPIO_ALT_FN_3_OUT) // SCLK
#define SG2_GPIO35_SSPTXD (35 | GPIO_ALT_FN_3_OUT) // SI
// #define SG2_GPIO39_SSPSFRM (39 | GPIO_ALT_FN_3_OUT) // CSn
#define SG2_GPIO41_SSPRXD (41 | GPIO_ALT_FN_3_IN) // SO
#define SG2_GPIO39_CC_SFRM 39
// #define SG2_GPIO39_CC_SFRM (39 | GPIO_ALT_FN_3_OUT) // CSn
#define SG2_GPIO22_CC_RSTN 22
#define SG2_GPIO114_CC_FIFO 114
#define IM2_GPIO115_CC_VREG 115
#define SG2_GPIO116_CC_CCA 116
#define SG2_GPIO0_CC_FIFOP 0
#define SG2_GPIO16_CC_SFD 16
#define CC2420_FIFO_IRQ IRQ_GPIO(SG2_GPIO114_CC_FIFO)
#define CC2420_CCA_IRQ IRQ_GPIO(SG2_GPIO116_CC_CCA)
#define CC2420_FIFOP_IRQ IRQ_GPIO(SG2_GPIO0_CC_FIFOP)
#define CC2420_SFD_IRQ IRQ_GPIO(SG2_GPIO16_CC_SFD)
3、ATMEGA128与CC2420连接:
OS_ASSIGN_PIN_list(CC_VREN, A, 5 ); // chipcon power enable
OS_ASSIGN_PIN_list(CC_FIFOP, E, 6 ); // fifo interrupt
OS_ASSIGN_PIN_list(CC_CCA, D, 6 ); //
OS_ASSIGN_PIN_list(CC_SFD, D, 4 ); // chipcon packet arrival
OS_ASSIGN_PIN_list(CC_CS, B, 0 ); // chipcon enable
OS_ASSIGN_PIN_list(CC_FIFO, B, 7 ); // chipcon fifo
// spibus assignments
OS_ASSIGN_PIN_list(MOSI, B, 2 );
OS_ASSIGN_PIN_list(MISO, B, 3 );
OS_ASSIGN_PIN_list(SPI_SCK, B, 1 );
4、S3C2410与CC2420的连接
SPIMISO
SPIMOSI
SPICLK
nSS_SPI
GPB0
GPB1
EINT0
EINT4
EINT5
EINT6