FPGA学习笔记（十）

74LS138使用Verilog表述方法

module ls138(
input clk,
input CI,
input A,
input B,
output reg S,
output reg CO
);

reg [1:0] num;

always@(*) num = A + B + CI;

always@(*)
	case(num)
	0:begin
		S = 0;
		CO = 0;
		end
	1:begin
		S = 1;
		CO = 0;
		end
	2:begin
		S = 0;
		CO = 1;
		end
	3:begin
		S = 1;
		CO = 1;
		end
	endcase

endmodule

使用两片74LS138合成片74LS238

module ls238(
input CI,
input [3:0] A,B,
output reg [3:0] S,
output reg CO
);

reg [1:0] b1,b2,b3,b4;

function [1:0] ls183;
input a,c,ci;
begin
	ls183 = a + c + ci;
end
endfunction

always@(*) b1 = ls183(A[0],B[0],CI);
always@(*) b2 = ls183(A[1],B[1],b1[1]);
always@(*) b3 = ls183(A[2],B[2],b2[1]);
always@(*) b4 = ls183(A[3],B[3],b3[1]);

always@(*) S = {b4[0],b3[0],b2[0],b1[0]};
always@(*) CO = b4[1];

endmodule

流水的灯实现代码

module led_R_W(
input rst,clk,
output reg [7:0] led
);

parameter CNT_MAX = 49_999_999;

reg [32:0] cnt;
reg [4:0] flag;

always@(posedge clk)
	if(rst)
		cnt <= 0;
	else if(cnt == CNT_MAX)
		cnt <= 0;
	else
		cnt <= cnt + 1;
		
always@(posedge clk)
	if(rst)
		flag <= 0;
	else if(flag == 9)
		flag <= 0;
	else if(cnt == CNT_MAX - 1)
		flag <= flag + 1;
		
always@(posedge clk)
	if(rst)
		led <= 0;
	else 
		led <= (1 << flag);

endmodule

数码管的单片显示

module nixie_tube(
input clk,rst,
output [7:0] seg7_sel,seg7_data
);

//50Mhz的时钟，每秒计数值
parameter NUM_MAX = 49_999_999;

//共阳极数码管，段选1~9编码
parameter [7:0] n0 = 8'b1100_0000;
parameter [7:0] n1 = 8'b1111_1001;
parameter [7:0] n2 = 8'b1010_0100;
parameter [7:0] n3 = 8'b1011_0000;
parameter [7:0] n4 = 8'b1001_1001;
parameter [7:0] n5 = 8'b1001_0010;
parameter [7:0] n6 = 8'b1000_0010;
parameter [7:0] n7 = 8'b1111_1000;
parameter [7:0] n8 = 8'b1000_0000;
parameter [7:0] n9 = 8'b1001_0000;
			 

reg [26:0] num;
reg [4:0] flag; 
reg [7:0] data;

//位选点亮最低位
assign seg7_sel = 8'b1111_1110;

//1s计数器
always@(posedge clk)
	if(rst)
		num <= 0;
	else if(num == NUM_MAX)
		num <= 0;
	else
		num <= num + 1;

//1秒标志位
always@(posedge clk)
	if(rst)
		flag <= 0;
	else if(num == NUM_MAX-1)
		flag <= (flag == 9)?0:flag + 1;

//第一位数码管显示的内容
always@(posedge clk)
	case(flag)
	0: data <= n0;
	1: data <= n1;
	2: data <= n2;
	3: data <= n3;
	4: data <= n4;
	5: data <= n5;
	6: data <= n6;
	7: data <= n7;
	8: data <= n8;
	9: data <= n9;
	default data <= 8'd1111_1111;
	endcase
		
//输出段选信号
assign seg7_data = data;

endmodule