Verilog实现非流水线乘法器

回头看了下之前写的乘法器,写的什么大奋,受不了重写一个,testbench在后面,等会会补个流水线写法

module multiplier #(parameter A_LEN = 8,B_LEN = 8)(
	input 									CLK,
	input 									EN,
	input										RSTN,
	input [A_LEN-1:0] 					Ai,
	input [B_LEN-1:0]						Bi,
	output [A_LEN+B_LEN-1:0]		 	Co,
	output									RDY);
	
	reg [A_LEN+B_LEN-1:0] 				Cout;
	reg [A_LEN+B_LEN-1:0] 				Co_reg;
	reg [A_LEN-1:0] 						Ain;
	reg [B_LEN-1:0]						Bin;
	
	integer 									mult_cnt;
	reg 										rdy;
	

		
	always @(posedge CLK or negedge RSTN) begin
		if (!RSTN) begin
        Cout <= 'b0;
		  Co_reg <= 'b0;
		  rdy <= 1'b0;
		  mult_cnt <= B_LEN;
		end else begin
			if(rdy == 1'b0) begin
				if(EN&&mult_cnt==B_LEN) begin
					rdy <= 1'b1;
					Cout <= 'b0;
				end
			end else if	(rdy == 1'b1) begin
				if (mult_cnt != 0) begin	
					if(Bi[mult_cnt-1]) 
						Cout <= (Cout<<1) + Ai;
					else 
						Cout <= (Cout<<1);
					mult_cnt = mult_cnt - 1;
				end else if(!mult_cnt) begin
					Co_reg <= Cout;
					Cout <= 'b0;
					rdy <= 1'b0;
					mult_cnt <= B_LEN;
				end	
			end	
		end	
	end		
		
	
	assign RDY = rdy;
	assign Co = Co_reg;
endmodule

这个仿真时序比我想的大了一点,好奇怪 

`timescale 1 ns/ 1 ns
module test ;
	reg				clk;
	reg				en;
	reg				rstn;
	reg[12:0]		ai;
	reg[11:0]		bi;
	
	wire [24:0]		co;
	wire				rdy;
	
	initial begin
		forever begin
			clk = 1;
			#10;
			clk = 0;
			#10;
		end
	end
	
	integer i;
	initial begin
		i = 0;
		rstn = 1'b1;
		rstn = 1'b0;
		#5;
		rstn = 1'b1;
		en = 1'b1;
	end
	
	always @(posedge clk) begin
		if(rstn&&!rdy) begin
			case(i)
				0 : begin
					ai <= 13'd34;
					bi <= 12'd10;
					i = i + 1;
				end
				1 : begin
					ai<= 13'd10;
					bi <= 12'd10;
					i = i + 1;
				end
				2 : begin
					ai <= 13'd1;
					bi <= 12'd1;
					i = i + 1;
				end
			endcase
		end
	end
	
	multiplier #(.A_LEN(13),.B_LEN(12))			My_mult(
		.CLK(clk),
		.EN(en),
		.RSTN(rstn),
		.Ai(ai),
		.Bi(bi),
		.Co(co),
		.RDY(rdy));
		
	initial begin
		forever begin
			#100
			if($time >= 1000) $finish;
		end
	end
	
endmodule