Chapter 20 Current Mirrors

Chapter 20 Current Mirrors

前面的章节在讲数字, 从这一章开始我们转向模拟了! 先介绍电流镜

The basic current mirror

请注意Chanel Length Modulation, 也就是Vds会导致Ids电流变化

Matching Current in the Mirror

Threshold Voltage Mismatch

即Vgs越大, Vdsat越大, 电流受Vth mismatch的影响越小

To attain high speed and to reduce the effects of threshold voltage mismatch, a large gate overdrive voltage should be used (remembering for a long-channel process that Vovn = VDS,sat = VGS - VTHN).

Drain-to-Source Voltage and Lambda

由Eq. 20.3可知, For good matching, the Vds for the current mirrors should be equal!

Layout Techniques to Improve Matching 一些layout技巧

把large W/L 分解成小块, 然后做成插指形状

mirror管子朝向orientation要一致

如果W不一致, 可以复制多个W串联来撑长W

Biasing the Current Mirror

VDD的变化会影响Current Mirror的Iref和Iout

Beta-Multiplier Reference

M2 W/L变大, 因此Vgs2小, Vgs1=Vgs2+Iref*R,

忽略沟道调整效应推导可得

这样 Iref和VDD无关了.

取K=4, 也称为constant-gm 偏置电路, 因为
$$g_m=\sqrt{2K{P}_{n}W/L{I}_{REF}}=\frac{1}{R}$$
这样gm只和R有关, 与MOS管性质无关了

注意constant-gm电路是一个正反馈, 之所以能稳定是因为R的存在, loop gain <1, 如果R很小 (例如外围加电阻, 寄生电容很大, M2类似short to ground) bias circuit是会震荡的.

constant gm能有效改善sensitivity of Iref over VDD 即
$$\frac{\partial I_{REF}}{\partial VDD}$$

Short-Channel Design

对于短沟道器件, drain current受 drain-to-source voltage 变化更大.

采用amplifier feedback, 提高output resistance, 能进一步提高Beta-multiplier circuit的power supply sensitivity

对于Op-amp loop最好只有一个high-Z点, 这样容易补偿. 在high-Z点加入MCP进行环路补偿. 同时把M2 结成diode形状, 这样能消除一个high-Z点, 代价就是gain有所降低.

Temperature Behavior

The point is that the temperature behavior of the reference current determines the temperature behavior of all mirrored currents.

For short-channel CMOS the change in Vthn with temperature is -0.6 mV/C°. Vth随着温度增加而减小!

Temperature coefficient 定义为
$$TC{I}_{REF}=\frac{1}{I_{REF}}\frac{\partial I_{REF}}{\partial T}$$
对于BGR(Beta-Multiplier Reference), 取适当的R值希望Temp Coefficient为零

Biasing in the subthreshold Region

Current Mirror工作在亚阈值区理论可行, 但电流得小, R得大, 实际问题是匹配性较差

Cascoding the Current Mirror

The simple cascode

casecode output resistance
$$R_o=(2+g_m{r}_o)r_o=g_{m}r{{}_o}^2$$
这里的gm是gm4

Low-Voltage(Wide-Swing) Cascode

普通的casecode, 其Vout最低值, 即M4的Vdrain=2Vgs=2(Vth+Vdsat)

这是因为M2的drain电压等于Vgs, 同时M3 diode连接, M4的gate电压是2Vgs, 因此M4 Drain=M4 Gate=2Vgs, 蛮大的!

Wide-Swing structure:

另外做一路MWS bias M4的gate. M4 的gate降为Vgs+Vdsat=2Vdsat+2Vth, 这样M4的drain就能最小为2Vdsat. MWS W/L=1/4.

注意在实际电路中, 还是要把MWS W/L做小到1/5, 这样M4的gate更高, M2的drain略大于Vdsat. 一般说来 Vds需要200mV over Vgs-Vth (Vdsat), 这样M2才能原理线性区, current mirror效果更好.

Wide-Swing short-Channel Cascode

对于短沟道器件, channel length modulation效应更加严重, 更需要保障Vds相同, Fig 20.32 design中的M1和M2的drain不同, M1 drain=Vgs, M2=Vdsat, 会造成current mirror mismatch差.

在M1的drain上添加M3, 来降低M1的drain, 提高current mirror精度

暴论: 对于所有wide swing的电路, 都应该加上M3这样的设计!

M1, M2 drain is 150mV over Vdsat, M3 接近triode region.

Regulated Drain Current Mirror

添加Op-amp 来regulate M2 drain 等于 M1 drain, 这样能增加输出阻抗, 和使M1,M2的matching更好.
$$R_{out}=g_m{r}_o^2\cdot A$$

实际常用电路如上图, MA1和MA2 确保M1和M2的drain为Vgs且相等. 当M2 drain下降时, MA2 start shutting off, M4 gate 上升, 弥补M2 drain下降. 且增加输出阻抗.

输出电压最小为Vdsat+Vgs

Biasing Circuit

利用前面beta-multiplier电路可做偏置电路, Vbias1, 2, 3,4 可做wide-swing current mirrors.

Vhigh, Vlow可用在Amplifier里来regulate MOSFET的drain.

Vncas和Vpcas可用于后面介绍的"floating current source"

对于casecode 输出, 可做folded cascode结构 and diode-connect the folded NMOS devices. (当然diode-connect PMOS也行)

对于short-Channel Bias Circuit

Floating Current Sources

在casecode structrure基础上添加MFCP和MFCN形成 floating current source. 目的是驱动MOP和MON大管子, 确定其电流. The addition of MFCN, for example, allows the voltage across the PMOS cascode structure to become Vbias1 (assuming that matching between the bias circuit and this circuit is perfect). The voltage across the NMOS cascode becomes Vbias4.