HDL—Verilog Language—Vectors—More replication

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.

给定五个1位信号（a、b、c、d和e），计算25位输出矢量中的所有25个成对1位比较。如果被比较的两个比特相等，则输出应该是1。

如果是直接去一位一位的写也是可以的，

out[24] = ~a ^ a; // a == a, so out[24] is always 1.

out[23] = ~a ^ b;

out[22] = ~a ^ c;

...

out[ 1] = ~e ^ d;

out[ 0] = ~e ^ e;

但很显然就不酷了，所以用位拼接把信号拼接起来然后直接使用按位异或就可以了。

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    // The output is XNOR of two vectors created by
    // concatenating and replicating the five inputs.
    // assign out = ~{ ... } ^ { ... };
    assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{5{a,b,c,d,e}};
endmodule