ARM架构异常模式进入和退出流程

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已于 2024-02-29 20:18:58 修改

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分类专栏： ARM架构文章标签： arm开发汇编

于 2024-02-29 19:59:12 首次发布

本文链接：https://blog.csdn.net/Albert_Swift/article/details/136379451

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文章详细描述了ARM920T处理器在进入和离开异常时的行为，包括保存指令指针、CPSR处理、异常模式设置以及异常退出时的PC调整。涉及的异常类型有Undef、SWI、IRQ、FIQ、PABT和DABT。还展示了部分代码示例，展示了上下文切换的过程。

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进入异常的处理流程（硬件完成）

Action on Entering an Exception进入异常时
While handling an exception, the ARM920T does following activities:

\1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered
from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4
or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from
THUMB state, then the value written into the Link Register is the current PC offset by a value such that the
program resumes from the correct place on return from the exception. This means that the exception handler
need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC,
R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or
THUMB state.

把被中断模式的下一条指令的地址(PC + 0x4/0x8)保存在LR_[某一种异常模式]寄存器中，

i. PC + 0x4

ii. PC + 0x8

Return Instruction	Return Instruction	Previous State	Previous State	Notes
		ARM R14_x	THUMB R14_x
BL	MOV PC, R14	PC + 4	PC + 2	(1)
SWI	MOVS PC, R14_svc	PC + 4	PC + 2	(1)
UDEF	MOVS PC, R14_und	PC + 4	PC + 2	(1)
FIQ	SUBS PC, R14_fiq, #4	PC + 4	PC + 4	(2)
IRQ	SUBS PC, R14_irq, #4	PC + 4	PC + 4	(2)
PABT	SUBS PC, R14_abt, #4	PC + 4	PC + 4	(1)
DABT	SUBS PC, R14_abt, #8	PC + 8	PC + 8	(3)
RESET	NA	–	–	(4)

\2. Copies the CPSR into the appropriate SPSR

SPSR_[某一种异常模式] = 被中断模式的CPSR

\3. Forces the CPSR mode bits to a value which depends on the exception

修改CPSR的M4-M0，进入异常模式

\4. Forces the PC to fetch the next instruction from the relevant exception vector

跳到向量表

退出异常时的处理流程（软件完成）

Action on Leaving an Exception

On completion, the exception handler:
\1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the
type of exception.)

a. PC = LR_[某一种异常模式] 减去某个offset值，

b. 比如，发生了SWI异常，可以在svc管理模式中，把R14_svc的值赋给PC，如果发生的IRQ异常，可以在irq中断模式中，把R14_irq减去4以后赋给PC，

Return Instruction	Return Instruction	Previous State	Previous State	Notes
		ARM R14_x	THUMB R14_x
BL	MOV PC, R14	PC + 4	PC + 2	(1)
SWI	MOVS PC, R14_svc	PC + 4	PC + 2	(1)
UDEF	MOVS PC, R14_und	PC + 4	PC + 2	(1)
FIQ	SUBS PC, R14_fiq, #4	PC + 4	PC + 4	(2)
IRQ	SUBS PC, R14_irq, #4	PC + 4	PC + 4	(2)
PABT	SUBS PC, R14_abt, #4	PC + 4	PC + 4	(1)
DABT	SUBS PC, R14_abt, #8	PC + 8	PC + 8	(3)
RESET	NA	–	–	(4)

\2. Copies the SPSR back to the CPSR

CPSR = SPSR_[某一种异常模式]

\3. Clears the interrupt disable flags, if they were set on entry

对于中断异常，清中断状态；

部分代码实现

do_undefined_instruction:
    /*context switching*/
    stmdb sp!,{r0-r12,lr}
    /*handle undefined instruction*/
    /*context switching*/
    ldmia sp!,{r0-r12,pc}^//^:CPSR = SPSR_[某一种异常模式]

do_software_interrupt:
    /*context switching*/
    stmdb sp!,{r0-r12,lr}
    /*handle software interrupt*/
    /*context switching*/
    ldmia sp!,{r0-r12,pc}^

do_prefetch_abort:
    /*context switching*/
    subs lr,#4
    stmdb sp!,{r0-r12,lr}
    /*handle prefetch abort*/
    /*context switching*/
    ldmia sp!,{r0-r12,pc}^

do_data_abort:
    sub lr,#8
    /*context switching*/
    stmdb sp!,{r0-r12,lr}
    /*handle data abort*/
    /*context switching*/
    ldmia sp!,{r0-r12,pc}^