Quartus联合modelsim和Signaltap仿真
工具:Quartus Ⅱ9.0、modelsim10.4
项目:流水灯
- 仿真项目文件(flowLed.v)
module flowLed
(
input clk, //系统时钟
input rst_n, //系统复位,低电平有效
output reg [7:0] led //8个LED灯
);
reg [26:0] count;
//流水灯计数器
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) //低电平状态
count <= 27'd0;
else if (count < 27'd1000_0000