UVM一个功能覆盖率的简单例子

一个功能覆盖率的简单例子

功能覆盖率的类型

在验证计划中编写test case时，需要编写功能覆盖率计划。一般而言，在验证环境中有4个地方可以编写coverage points.

F1 : Functional coverage points are very near the randomization

F2 : Functional coverage points are sampled at input interface of DUT

F3 : Functional coverage points which sample internal DUT states

F4 : Functional coverage points which sample output interface of DUT

功能覆盖率的简单例子：

 

 

//+++++++++++++++++++++++++++++++++++++++++++++++++
//   DUT With Coverage
//+++++++++++++++++++++++++++++++++++++++++++++++++
module simple_coverage();

logic [7:0]  addr;
logic [7:0]  data;
logic        par;
logic        rw;
logic        en;
//=================================================
// Coverage Group
//=================================================
covergroup memory @ (posedge en);
  address : coverpoint addr {
    bins low    = {0,50};
    bins med    = {51,150};
    bins high   = {151,255};
  }
  parity : coverpoint  par {
    bins even  = {0};
    bins odd   = {1};
  }
  read_write : coverpoint rw {
    bins  read  = {0};
    bins  write = {1};
  }
endgroup
//=================================================
// Instance of covergroup memory
//=================================================
memory mem = new();
//=================================================
// Task to drive values
//=================================================
task drive (input [7:0] a, input [7:0] d, input r);
  #5 en <= 1;
  addr  <= a;
  rw    <= r;
  data  <= d;
  par   <= ^d;
  $display ("@%2tns Address :%d data %x, rw %x, parity %x",
     $time,a,d,r, ^d);
  #5    en <= 0;
  rw    <= 0;
  data  <= 0;
  par   <= 0;
  addr  <= 0;
  rw    <= 0;
endtask
//=================================================
// Testvector generation
//=================================================
initial begin
  en = 0;
  repeat (10) begin
    drive ($random,$random,$random);
  end
  #10 $finish;
end

endmodule

In the example we have covergroup memory which basically gets sampled on every posedge of en, and it samples address for three ranges, parity for even and odd, and finally rw for read and write.

和module/program/interface, coverage 可以用new()实例化，在每个en的边沿上所有的数据被采样存储在仓库（bins）中。

编写Makefile 文件

all:
    vcs -sverilog -R simple_voerage.sv -debug_all

cov:
    dve -covdir simv.vdb&

urg:
    urg -dir simv.vdb

clean:
    rm -rf *.log simv.* DVEfiles urg* csrc *.key simv

首先，运行make all 生成覆盖率文件simv.vdb文件，然后运行make dve，用dve图形化的方式查看代码覆盖率。

参考文献：

[1] http://www.asic-world.com/systemverilog/coverage1.html#Simulation_:_Coverage

[2] http://www.asic-world.com/systemverilog/coverage.html