/**********************************************************************
* ?2008 Microchip Technology Inc.
*
* FileName: main.c
* Dependencies: Header (.h) files if applicable, see below
* Processor: dsPIC33Fxxxx
* Compiler: MPLAB?C30 v3.02 or higher
*
* SOFTWARE LICENSE AGREEMENT:
* Microchip Technology Incorporated ("Microchip") retains all ownership and
* intellectual property rights in the code accompanying this message and in all
* derivatives hereto. You may use this code, and any derivatives created by
* any person or entity by or on your behalf, exclusively with Microchip's
* proprietary products. Your acceptance and/or use of this code constitutes
* agreement to the terms and conditions of this notice.
*
* CODE ACCOMPANYING THIS MESSAGE IS SUPPLIED BY MICROCHIP "AS IS". NO
* WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
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* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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* ADDITIONAL NOTES:
* Code Tested on:
* Explorer 16 board with dsPIC33FJ64GS610 device
**********************************************************************/
#if defined(__dsPIC33F__)
#include "p33Fxxxx.h"
#endif
//Macros for Configuration of Fuse Registers:
//Invoke macros to set up device configuration fuse registers.
//The fuses will select the oscillator source, power-up timers, watch-dog
//timers etc. The macros are defined within the device
//header files. The configuration fuse registers reside in Flash memory.
//External Oscillator
_FOSCSEL(FNOSC_PRI); // Primary (XT, HS, EC) Oscillator
_FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_XT);
// Clock Switching is enabled and Fail Safe Clock Monitor is disabled
// OSC2 Pin Function: OSC2 is Clock Output
// Primary Oscillator Mode: XT Crystanl
//
Internal FRC Oscillator
//_FOSCSEL(FNOSC_FRC); // FRC Oscillator
//_FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_NONE);
// Clock Switching is enabled and Fail Safe Clock Monitor is disabled
// OSC2 Pin Function: OSC2 is Clock Output
// Primary Oscillator Mode: Disabled
//_FWDT(FWDTEN_OFF); // Watchdog Timer Enabled/disabled by user software
//
int main(void)
{
/* Configure Oscillator to operate the device at 40Mhz */
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// Fosc= 7.37M*43(2*2)=80Mhz for 7.37M input clock
PLLFBD=41; // M=43
CLKDIVbits.PLLPOST=0; // N1=2
CLKDIVbits.PLLPRE=0; // N2=2
OSCTUN=0; // Tune FRC oscillator, if FRC is used
// Disable Watch Dog Timer
RCONbits.SWDTEN=0;
// Clock switching to incorporate PLL
__builtin_write_OSCCONH(0x03); // Initiate Clock Switch to Primary
// Oscillator with PLL (NOSC=0b011)
__builtin_write_OSCCONL(0x01); // Start clock switching
while (OSCCONbits.COSC != 0b011); // Wait for Clock switch to occur
// Wait for PLL to lock
while(OSCCONbits.LOCK!=1) {};
/* Configure Auxillary Oscillator to setup the PWM clock for 120Mhz */
// ACLK = (REFCLK * M) / N
// ACLK = ((FRC * 16) / APSTSCLR ) = (7.37 * 16) / 1 = ~ 120MHz*/
ACLKCONbits.FRCSEL = 1; // FRC provides input for Auxiliary PLL (x16)
ACLKCONbits.SELACLK = 1; //Auxiliary Oscillator provides clock source for PWM
ACLKCONbits.APSTSCLR = 7; // Divide Auxiliary clock by 1
ACLKCONbits.ENAPLL = 1; // Enable Auxiliary PLL
while(ACLKCONbits.APLLCK != 1); // Wait for Auxiliary PLL to Lock
/* Remap the pins for fault and current limit input */
__builtin_write_OSCCONL(OSCCON & ~(1<<6));
__builtin_write_OSCCONL(OSCCON | (1<<6));
/* Configure PWM generator 1 for Independent Fault Mode */
// Enable the PWM interrupts
IFS5bits.PWM1IF=0; // Interrupt flag status register
IEC5bits.PWM1IE=1; // Interrupt request is enabled
PTCON2bits.PCLKDIV = 0;// Divide by 1, maximum PWM timing resolution
PTPER = 1000; // Configure PTPER register for PWM frequency of 1.04ns
MDC = 500; // Duty cycle of 50%
// PWM1 Fault and Current Limit Control register
FCLCON1bits.IFLTMOD = 1; // Independent Fault Mode
FCLCON1bits.CLSRC = 0x1C; // Fault input pin 21
FCLCON1bits.CLPOL = 1; // The selected current-limit source is active-lo
FCLCON1bits.CLMOD = 1; // Current-Limit mode is enabled
FCLCON1bits.FLTSRC = 0x1D; // Fault input pin 22
FCLCON1bits.FLTPOL = 1 ; // The selected Fault source is active-lo
FCLCON1bits.FLTMOD = 1; // The PWM is configured for cycle by cycle mode
// PWM1 I/O Control register
IOCON1bits.PENH = 1; // PWM1H is controlled by PWM module
IOCON1bits.PENL = 1; // PWM1L is controlled by PWM module
IOCON1bits.POLH = 0; // PWMxH pin is active-high
IOCON1bits.POLL = 0; // PWMxL pin is active-high
IOCON1bits.PMOD = 0; // PWM I/O pin pair is in the Complementary Output mode
IOCON1bits.FLTDAT = 0; // PWM1H and PWM1L are driven LOW on occurance of Fault and Current limit respectively
// PWM1 Control register
PWMCON1bits.FLTSTAT = 0; // cleared so no interrupt pending
PWMCON1bits.CLSTAT = 0; // cleared so no interrupt pending
PWMCON1bits.TRGSTAT = 0; // cleared so no interrupt pending
PWMCON1bits.FLTIEN = 1; // Fault Interrupt enabled
PWMCON1bits.CLIEN = 1; // Current Limit Interrupt enabled
PWMCON1bits.TRGIEN = 0; // Trigger event interrupts disabled
PWMCON1bits.ITB = 0; // PTPER register provides timing for PWM1 generator
PWMCON1bits.MDCS = 1; // MDC provides duty cycle information
PTCONbits.PTEN = 1; // Enable the PWM Module
while(1);
}
void __attribute__((__interrupt__,no_auto_psv)) _PWM1Interrupt(void)
{
IFS5bits.PWM1IF = 0; //Clear the interrupt flag
if(PWMCON1bits.FLTSTAT ==1)
PWMCON1bits.FLTSTAT = 0; // Clear the fault status bit
if(PWMCON1bits.CLSTAT ==1)
PWMCON1bits.CLSTAT = 0; // Clear the current limit status bit
}
dsPIC33F之PWM1 Interrupt
最新推荐文章于 2024-07-21 21:19:55 发布